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2018-12-03mb/sifive/hifive-unleashed: Use if (IS_ENABLED(...))Jonathan Neuschäfer
"if" is preferable over "#if", because it lets the compiler perform syntax and type checks even if CONFIG_CONSOLE_SERIAL is disabled. Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-03sb/intel/lynxpoint: Move `HAVE_SMI_HANDLER` to southbridge KconfigTristan Corrick
All Lynx Point board select this, and none build without it. Change-Id: I4b59b10ee985cff5a8e1442677d36b0be88cf437 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/common: Create a common PCH finalise implementationTristan Corrick
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/lynxpoint: Make the finalise handler commonTristan Corrick
The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03mb/google/poppy/variant/nocturne: increase touch panel power-on delayNick Vaccaro
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29988 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B groupShelley Chen
We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03mb/google/fizz/variants/karma: Update USB port infoDavid Wu
Update USB port info according to the schematic file. BUG=none BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03mb/google/fizz/variants/karma: Disable native SD card controllerDavid Wu
This change selects Kconfig option to disable native SD card controller in ACPI tables. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial numberMichał Żygowski
Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration is different when a external PCIe device is connected to mPCIe2 slot which is routed to first PCIe bridge. The first NIC is then assigned BDF 2:0.0, because it is connected to the second PCIe bridge. Read the secondary bus number from the NIC PCIe bridge before attempting to read MAC adress and calculating serial number. Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03mb/google/dragonegg: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/broadwell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30cpu/intel/model_206{5,a}x: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29886 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/haswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications the CPU. Generate PPKG in SSDT. Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29885 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30arch/power8: Rename to ppc64Jonathan Neuschäfer
POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30broadcom: Remove SoC and board supportPhilipp Deppenwiese
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29google/kahlee/variants/aleena: Set STAPM values.Lucas Chen
According to aleena thermal testing to set STAPM values. skin scalar for 80%. time constant for 2500s. power limit for 7.8w. BUG=b:72979852 TEST=test build for thermal check. Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part NumberLucas Chen
Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29mb/google/octopus: Create Casta variantKarthikeyan Ramasubramanian
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-11-29{mb/cubieboard,soc/intel/quark}: Remove define __SIMPLE_DEVICE__Elyes HAOUAS
Remove the __SIMPLE_DEVICE__ define from files used only in romstage. This is not required since romstage always defines __SIMPLE_DEVICE__. Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29821 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29882 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29mediatek/mt8183: Add MT6358 PMIC supportHsin-Hsiung Wang
PMIC provides power features like auxadc, buck/ldo, interrupt-controller..etc BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29422 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/google/kahlee: Update vBIOS used for aleenaRichard Spiegel
The aleena board uses a display that's not compatible with current VBIOS. A VBIOS specific for aleena has been merged into blobs, so modify Kconfig so that it loads the new VBIOS when building aleena, but load original VBIOS for all other boards under kahlee folder. BUG=b:112618193 TEST=Build each board under kahlee, one at a time. After each build, opened build/config.h and searched VGA_BIOS_FILE to verify that the string only changed for aleena, all other boards remained with original string. Change-Id: Iccd0853692680908d951edd142a2d8e13a561391 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28src/{mainboard,southbridge}: Remove commented include linesElyes HAOUAS
Change-Id: Ie06ae528ade3e06ae880b488628692ce43c30f5a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29845 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/hp/compaq_8200_elite_sff: Fix SATA port mapPatrick Rudolph
Assign correct SATA port map. Tested on HP8200: All SATA ports are now usable in GNU/Linux. Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/29855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-27mb/google/octopus/var/phaser: Deprecate board id 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of code in variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-27mainboard/google/reef: Bump mainboard mem versionKane Chen
This change is to bump fsp_memory_mainboard_version in order to trigger MRC full training BUG=b:119481870 CQ-DEPEND=CL:*716558 BRANCH=reef, coral TEST=make sure MRC retraining is triggered and the MRC cache is updated to newer version. Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/29647 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/intel/icelake_rvp: Enable HDA audio supportAamir Bohra
This patch enables HDA audio support on icelake rvp. Add ALC700 codec verb table and selects SOC_INTEL_COMMON_BLOCK_HDA_VERB config to detect and initialize codec configuration as specified in verb table. BUG=none TEST=verify codec is listed and audio playback is working Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27mb/intel/icelake_rvp: Add EC acpi support codeAamir Bohra
This implementation adds below changes: 1. Add chrome ec asl support for iclrvp. 2. EC SCI, SMI, S3/S5 wake events. 3. Wake pin and EC SMI GPE confiiguration. Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29797 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/intel/icelake_rvp: Include cpu.asl in DSDT ACPI tableAamir Bohra
This implementation adds support of PNOT method included in cpu.asl. It is needed to notify CPU APCI device to re-evaluate the _CST table for list of supported C-states. Change-Id: I135cc3aa32a912c8ad3449d063d533f8873fcc94 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Tested on Intel D945GCLF, still boots fine but breaks S3 resume support because it hangs on SMI. Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27mb/google/dragonegg: Enable audioSubrata Banik
BUG=b:116191230 BRANCH=None TEST=1. verified boot beep support at depthcharge. Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29753 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable trackpadSubrata Banik
BUG=b:112282079 BRANCH=None TEST=1. run evtest and make sure trackpad shows up in list 2. Able to wake system from S3 using trackpad Change-Id: I86d6b7815147d558065611604363bb607119c154 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29752 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable ps2 keyboardShelley Chen
BUG=b:112332115 BRANCH=None TEST=ensure at bootup that /sys/devices/pnp0/00:05 exists and driver link to '../../../bus/pnp/drivers/i8042 kbd' Also, can now see keyboard in evtest. Change-Id: I2a6b382be84bc5201beafe21ff8ddee3738bc5c2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29750 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Add initial mainboard code supportAamir Bohra
This patch includes support for both ICL ES0 and ES1 samples. Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md TEST=Able to build and boot dragonegg. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27mb/google/poppy/variants/nami: Enable g2touch touchscreen deviceCrystal Lin
This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/fizz/variants/karma: Disable SD controller and update GPIODavid Wu
The SD cardreader is on USB bus, not on SDIO/SDXC. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mb/google/fizz/variants/karma: Enable touchscreen wakeupDavid Wu
Set GPIO GPP_B4 to high to enable touchscreen wakeup. BUG=b:119594783 BRANCH=master TEST=DUT can wake up with touchscreen. Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mainboard/google/octopus/variants/ampton: Decrease I2C CLK frequencyCarl Yang
The touchpad and touch-panel CLK frequency should be smaller than 400 kHz which described in spec. Overwrite i2c speed parameters by overridetree.cb BUG=b:119540449 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage flash bios and check the touchpad i2c frequency meets the spec. Change-Id: I32c3e1bbfc2cdf39e9b7865a69996e54346d5f93 Signed-off-by: Carl Yang <carl_yang@asus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mb/google/octopus/var/bobba: Deprecate board id < 2Furquan Shaikh
This change deprecates boards with id < 2. It updates touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable GPIO at runtime. Additionally, it configures old enable GPIO as NC. BUG=b:119885949 Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus/var/fleex: Deprecate bid 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboardFurquan Shaikh
This change updates the configuration of GPIO_178 to be active low as per latest revision on different octopus variants. This effectively: 1. Gets rid of early_gpio_table in different variants -- phaser, meep, fleex, bobba. 2. Deprecates board id < 2 for bobba, board id < 1 for fleex and phaser. 3. Adds special early_gpio_table in yorp which has GPIO_178 as an active high signal. BUG=b:119885949 Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus: Configure all debug header lines as NCFurquan Shaikh
This change configures all the pads going to debug header as not connected. BUG=b:111569213 BRANCH=None TEST=None Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/intel/icelake_rvp: Add USB port capablity informationAamir Bohra
This implementation adds USB port capablity map for ICL-U and ICL-Y RVP. Change-Id: I20bb43c47439df0a25ff148eae2b3e0546e4bc63 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer
This mainboard has four connected PCIe devices. The required root ports are switched on and configured. Change-Id: I82b13e1d245a172762ebd689ae136a762027033f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29810 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 06:43:29 +0000