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2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15qemu: fix ioapic reservationGerd Hoffmann
The slightly hackish ioapic ressource reservation is needed for i440fx emulation only, for q35 the ich9 southbridge driver handles this just fine. [ Side note: The i440fx chipset emulated by qemu is pimped up with alot of stuff which never existed on real hardware, which leads to tweaks like this one. ] Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VDRudolf Marek
Use the same HD Audio [1] verb table for the Realtek ALC887-VD audio chip as the one set up by the proprietary vendor BIOS. Linux’ ALSA exposes this pin configuration under the virtual filesystem sysfs. /sys/class/sound/hwC1D0/init_pin_configs The script `alsa-info.sh` [2][3] is able to decode the table. Only one channel audio playback (rear connectors) is tested [4], which worked already before. [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html [3] http://alsa-project.org/main/index.php/Help_To_Debug [4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`Paul Menzel
The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the pin configuration needs to be adapted when taking this file as a template for a new port. If it was board independent, a default chip configuration could be used and shared between all boards, which is unfortunately not the case. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 secondsPeter Stuge
The ThinkPad keyboard controller sometimes needs a while in order to initialize, so let's ask SeaBIOS to wait for it. This change ensures that the internal keyboard always functions correctly on the ThinkPad when coreboot is built with SeaBIOS as payload. Change-Id: I562475ec98b0c1f5d0debf6e9b597748a420f068 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15qemu: reserve portsGerd Hoffmann
QEMU has a bunch of non-standard virtual devices on various I/O ports. Allocate resources for them so the coreboot resource management knows those ports are used. Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15AMD Kabini: Split DSDT into common sectionsMike Loptien
Split the Family16 (Kabini) DSDT file into logical regions. Olive Hill is the only mainboard and Kabini is the only NB/CPU currently using Family16 AGESA code. Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3821 Tested-by: build bot (Jenkins)
2013-08-13dmp/vortex86ex: Initialize Reatek ALC262 audio codecAndrew Wu
Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone did not work. With the new logic it does. Now line-in,line-out and microphone all work. The verb data table is generated by Realtek. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3855 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-09intel/sandybridge intel/bd82x6x: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-08ASUS F2A85-M: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the F2A85-M DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the F2A85-M dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for F2A85-M. Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3805 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08AMD Thatcher: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the Thatcher DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the Thatcher dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Thatcher. Change-Id: Ie44a32959cc547840914365e872416d4624d33df Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)Bruce Griffith
Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-06AMD Olive Hill: Change SB800 references to YangtzeBruce Griffith
Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3815 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Add HUDSON_LEGACY_FREE flagBruce Griffith
Olive Hill does not have a Super I/O or keyboard controller. Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Remove default VBIOS vendor/device IDBruce Griffith
The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3816 Tested-by: build bot (Jenkins)
2013-08-05AMD Olive Hill: Enable HDMI audio setting in build optionsBruce Griffith
Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3814 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Eliminate unnecessary memory copyBruce Griffith
Eliminate an unnecessary copy of the DDI descriptor list and the PCIe port descriptor list. As descriptor tables, these tables do not need dynamic updating and should be used from ROM without runtime copying. There will be a corresponding patch for AGESA that adds CONST modifiers to function parameters that are pass-by-reference "IN" values (read-only pointers). Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3818 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Add new AMD mainboard using Kabini processorSiyuan Wang
Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-07-31Drop unused EXTERNAL_MRC_BLOBStefan Reinauer
The Kconfig variable EXTERNAL_MRC_BLOB is not used. Drop it. Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3829 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-29kontron/ktqm77: Update cmos checksum rangeNico Huber
Change-Id: I08e56b4a1c56128c6d4beb751979c5b99cdae829 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29kontron/ktqm77: Squeeze more fan options into cmos.layoutNico Huber
Change-Id: Ic660efec519a9a970ec5a8832fd1dd8c9516318f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3775 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-26AMD Parmer: Fix file permissions on asl files in mainboardKimarie Hoot
Removed the execute bit on all files in mainboard/amd/parmer/acpi Change-Id: I85ffa66e0beb9c4bfe826b72968f7f633c224487 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3807 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-26emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO in qemu-q35 emulation To enable MMIO style access, add (move) explicit PCI IO config write in the bootblock. As there is no northbridge/x/x/bootblock.c file, a mainboard/x/x/bootblock.c file is added for this purpose. Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3599 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-18SMBIOS: Clarify prompts and help texts for Serial and Version NumbersPeter Stuge
Change-Id: If1fa39db79eeecbef90c8695143d2fe2adf2f21a Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3732 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-17Revert "lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String"Peter Stuge
This reverts commit cd24e3f6a7adecfc9d3b2a2dd2f81d84acffa91b. Change-Id: I3d1fec75d99d0b480a47b4d433c14a681831d9f8 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3778 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-07-17lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM StringPeter Stuge
The Linux thinkpad_acpi.c driver looks for this string while reading information about the system it is running on. This commit does not make the module load but it is one of several things that the module looks for on a ThinkPad. The use of 3 defines for the serial number template seems odd but it's done in a way that eliminates magic numbers, yet avoids use of strcpy, strlen, strindex, strchr, or strspan: we can have some correctness assured at compile time. Also, the defines can be copy/pasted for other mainboards and we should void errors due to people not changing magic numbers. Change-Id: Ief5f28d2e27bf959cb579c4c8eea9eecc9a89a7c Signed-off-by: Peter Stuge <peter@stuge.se> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-16beaglebone: Get rid of a redundant CBFS_ROM_OFFSET.Gabe Black
CBFS_ROM_OFFSET was declared in both the am335x config and the beaglebone config. This removes it from the beaglebone config. Change-Id: I657cb8e83a1ee961d8bdc995a41f303920bc53f9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-07-16AMD Fam15tn: Split DSDT into common sectionsSteve Goodrich
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/3629 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-15beaglebone: Put some code in romstage.c so we can tell if it ran.Gabe Black
The placeholder code in beaglebone's romstage.c didn't do anything, it just immediately tried to load the RAM stage and jump into it. That doesn't currently work, and there's no indication whether you actually successfully got into the ROM stage or not. This change adds a few lines which initialize the console and say "Hi" so that we can tell that the ROM stage is running. Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14SMBIOS: Allow overriding default Manufacturer and Product namesPeter Stuge
The vendor and part name from coreboot is normally stored in these SMBIOS structure fields, but it can be useful to override them. On Lenovo ThinkPads an override is e.g. needed to convince the Linux thinkpad_acpi.c driver that it is actually running on a ThinkPad. Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-14lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVOPeter Stuge
This is needed for the Linux thinkpad_acpi.c driver to load. Change-Id: I3d9549395556ffb0abfc3cb52b3d01386c34caa5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3731 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-13lenovo/x60: Move mainboard_enable() code into a mainboard_init()Peter Stuge
mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: Iaf9187532a1e432b991260201b95dda85cc312c5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Redo the display port bridge initialization code.Gabe Black
The display port bridge on pit is different from the one on snow and needs to be initialized differently. Instead of waiting for the chip to come up on its own and assert the hotplug detect, we need to access it over i2c and get it up and running ourselves. Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Enable the ps8625 driver.Gabe Black
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop setting up the hardware dp hotplug detect in ROM stage too.Gabe Black
This was removed from ramstage a little while ago and should have been removed from here as well. Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: add panel to the list of things to be powered up by the PMICRonald G. Minnich
This appears to be needed, though we have no way to test yet. Change-Id: I39033581011e056258193f2cdff78814361a8d55 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos: Prevent unexpected reboots in resume.Hung-Te Lin
In resume path, if memory setup takes too long without setting PS_HOLD, EC watch dog may power off or reboot the system. To prevent that, we should enable PS_HOLD in same timing as cold boot - right before starting memory setup. Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the tps65090 functions and adjust the hotplug detect line.Gabe Black
The functions which manipulated the tps65090 were removed a while ago because it isn't accessible directly from the AP, it's on an I2C bus that has to be accessed by the EC on our behalf. Now that that capability has been added, we can rewrite the small portion of the the tps65090 we actually used but using the EC passthrough commands. Also, we should not be configuring the hardware display port hotplug detect line since we're using it as a GPIO for other purposes. The GPIO we're using instead defaults to being an input, but to be safe we should probably explicitly configure it as one anyway. Change-Id: I7f8a8a767e3cccb813513940a5feceea482982f5 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Correct EC device in mainboard configuration.Hung-Te Lin
The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C. Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Setup EC on SPI2.Hung-Te Lin
The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: update I2C4 speed constantDavid Hendricks
Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Configure the pinmux for the i2c busses that are connected on pit.Gabe Black
Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554) Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5250: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Simplify early / bootblock console codeStefan Reinauer
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the snow GPIO indexes with ones for pit.Gabe Black
The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Remove the MAX_CPUS option.Gabe Black
The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop compiling in the max77686 driver on pit.Gabe Black
That part isn't used on pit. Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop calling tps65090 functions until we can call through the EC.Gabe Black
On pit, the tps65090 is connected to the EC and has to be accessed by proxy. Until we have that implemented, this change removes calls to tps69050 which will never succeed, and stops compiling in the driver. Change-Id: I7218f85f9f26623bd13aaaf8ded0638b3b2f874a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>