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2017-12-07mainboard/intel/glkrvp: Ignore Audio DMIC IOSSTATESathyanarayana Nujella
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice. So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that clock is ON in S0ix state. BUG=None TEST=put DUT in S0ix, verified DMIC_CLK in scope when wov capture path is ON Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07google/gru: Add SKU ID for ScarletJulius Werner
Scarlet has SKU detection strapping pins now. This patch adds the code to read them. BUG=b:69373077 Change-Id: I8d889a845950923bc7b5be9b79792cf3c8b6b8ad Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22697 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/*/*/Kconfig: Remove default MMCONF_BASE_ADDRESS on Sandy BridgeArthur Heymans
Change-Id: I6f0d6d7fefc77fb05cdb629d09de8cb72496a9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-06mb/google/poppy: Remove variant_cros_gpios from variantsFurquan Shaikh
Variants nautilus and soraka currently provide the exact same definition for variant_cros_gpios as provided by the baseboard. This change removes the function defintions from variants so that the weak definition in baseboard can be used. Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22705 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy: Add config option for camera ACPI supportFurquan Shaikh
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow variants to define ACPI tables for camera support. It also prevents boards that do not need this from unnecessarily providing dummy files for camera ACPI support. Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*Furquan Shaikh
Change the prefix for TPM options from POPPY_USE_* to VARIANT_HAS_*. This makes it clear that these are variant specific options. Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*Furquan Shaikh
In order to allow variants to select different Kconfig options, this change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be selected by each variant in Kcnonfig.name. Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Remove dynamic disabling of TPMFurquan Shaikh
This change removes the dynamic disabling of TPM based on config options. Poppy and its variants will have only one type of TPM supported and so there is no need to update it dynamically. Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy/variants/soraka: Disable SPI TPMFurquan Shaikh
Soraka is no longer using SPI TPM. This change disables GSPI0 in device tree and updates gpio config accordingly. Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Disable SPI TPMFurquan Shaikh
Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in device tree and udpates gpio configuration accordingly. Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06google/kahlee: Set USB OC pinsMarc Jones
Set the USB over current pins for the Grunt baseboard and Kahlee mainboard. Removes the ACPI ASL OC code, which is not used on Stoney Ridge SOC. BUG=b:69229635 TEST=Build and boot Kahlee. Not tested with OC test fixture. Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-05google/gru: update RAMID tableLin Huang
There is some confusion with old RAMID table, make it clear, and let's no longer tangle it in future. Change-Id: I44215b4a6668074575a5df691ac1ff8fa3d15492 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-05mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep SxFurquan Shaikh
This change updates device tree deep_sx_config to disable internal pull-down on AC_PRESENT. BUG=b:69983729 Change-Id: I041900a5262f8fd920856f126185329242a0639a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05mb/hp/8460p: Add TPM supportBill XIE
After applying this change, /dev/tpm0 is visible inside GNU/Linux with kernel 4.9.51-1 from Debian, and there is a menu item shown inside SeaBIOS' (master only) interface if ESC is pressed. The TPM is confirmed working with [Heads](https://github.com/osresearch/heads). Change-Id: I3b845928954d203d1c3608b6704fedbd590e1fa9 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-04mb/google/fizz: Enable Wake-on-Lan featureGaggery Tsai
This patch enables WOL feature. BUG=b:69290148 BRANCH=None TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL packet. Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-02google/reef: Fix whitespace inconsistency in coral codePatrick Georgi
BUG=none BRANCH=none TEST=none Change-Id: I4e61f1327027c5100773e2b837f439a939807e72 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02google/reef: add more USB tuning for coral variantsPatrick Georgi
Lava numbers are in. BUG=b:69990330 BRANCH=none TEST=verified that USB signal is within spec Change-Id: I7416ec8d058271700ebe43f8d92af61c6c0d6b42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02mainboard/google/kahlee: Remove usb_oc.asl filesMartin Roth
These files aren't needed for the overcurrent functionality. BUG=b:69305596, b:69229635 TEST=Build Grunt & Kahlee. Overcurrent wasn't yet enabled so no other testing was needed. Change-Id: I8dcd50a249e387ccf1142949b359cee09942460a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-02mainboard/google/kahlee: Add Baseboard GPIOsMartin Roth
Add initial baseboard GPIOs based on grunt schematics. BUG=b:69305596 TEST=Build grunt Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-01mainboard/google/kahlee: Update Kconfig string used in makefilesMartin Roth
Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either is valid, but since we use parentheses everywhere else, it's better to be consistent. BUG=b:69691210 TEST=Build grunt & kahlee Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22656 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-30mb/google/poppy/variants/nautilus: Disable DPTFFurquan Shaikh
This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mainboard/google/fizz: Disable DPTF active policyDavid Wu
Use EC to perform FAN control. BUG=b:67487721,b:69404739,b:64439568 BRANCH=master TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: I3394d3af9cbdb3eab1f18254909f60e2704735c3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mainboard/compulab: add support for CompuLab Intense-PCHal Martin
Add coreboot support for CompuLab Intense-PC (Ivy Bridge) Modifications: - Memory SPDs have been fixed to detect both installed SODIMM modules - Full-height Mini-PCIe slot defaults to PCIe mode - mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA Tested (Xubuntu 17.10/Linux 4.13 where applicable): - 2+2GB DDR3-1600 SODIMMs pass memtest - 4+4GB DDR3-1600 SODIMMs pass memtest - 4+8GB DDR3-1333 SODIMMs pass memtest - 8+8GB DDR3-1333 SODIMMs pass memtest - Booting via USB working (with no SATA HDD present) - Booting to main SATA HDD working - DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS) - DisplayPort and HDMI dual-head working in Linux - Mini-PCIe devices (half/full-height) detected in Linux - mSATA working (when chosen using ENABLE_MSATA) - Onboard Intel 82579 GbE working - Secondary Realtek 8111 GbE working - Rear eSATA ports working - Onboard analog audio output working - HDMI audio output working - USB 3.0 working - Suspend to RAM (S3) working, but not tested extensively - Mini PCIe WiFi - FACE module FM-4USB (4 USB 2.0 ports) Disabled/unsupported: - TPM (BTO option, not included in base config) - FACE modules: - FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED - FM-SER (serial) NOT SUPPORTED/TESTED - FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED - FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED - FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED - FM-VC (video capture) NOT SUPPORTED/TESTED - FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED Not tested: - RS-232 Product information: http://www.fit-pc.com/web/products/intense-pc/ Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-30intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-30mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeCSubrata Banik
PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30mb/google/nautilus: add synaptics touch screen supportChris Wang
Add synaptics touchscreen in the device tree so that the correct ACPI device is created. BUG=b:66462881 BRANCH=master TEST=compiled/verify the touchscreen works Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-29google/kahlee: Add SPD functionMarc Jones
Add the mainboard_spd_read function in romstage and call the variants function. Grunt is the baseboard and has soldered down memory, so add it for the default weak SPD functions and build the SPDs in cbfs. Kahlee overrides the weak SPD function and falls back to the soc I2C SPD functions. BUG=b:67845441 TEST=Build and boot Kahlee. Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29google/kahlee: Rename board_id to memory_skuMarc Jones
The GPIOs used in board_id are meant to indicate the memory configuration. Rename board_id to memory_skus. Report the board_id received from the EC. BUG=b:69649438 Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22561 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29mb/google/poppy/variants/nautilus: Disable camera devicesFurquan Shaikh
This change disables camera devices until camera support is properly added for nautilus. Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29mb/google/poppy: Add variant support for camera aslFurquan Shaikh
This change adds infrastructure to allow variants to define their own camera.asl file. - Poppy and soraka use the one provided by baseboard. - Dummy file is added for nautilus since it does not have camera support enabled yet. TEST=Verified that DSDT table remains the same with and without this change. Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28google/scarlet: support kd097d04 panelLin Huang
Support kd097d04 dual mipi panel on Scarlet. Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28google/gru: correct backlight gpioLin Huang
it uses backlight enable pin as backlight gpio currently, correct it and define the right backlight gpio. Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: support dual mipi dsiLin Huang
Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang
Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settingsChris Wang
Change IA/GT/SA slow slew rate settings. System's audible noise will be reduced with them. - Slow slew rate for IA/GT/SA : fast/16 - Fast PKG C-state ramp for IA/GT/SA: disabled BRANCH=master BUG=none TEST=compiled/verified Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_tableDivya Chellap
On shutdown, Soraka enters Deep S5 and not S5 state. Setting pad reset config of a gpio to RSMRST will not preserve the gpio config across deepSx and the gpio should be configured again. The WLAN_PE_RST signal should be brought up early in the bootflow for giving the device enough time to initialized before PCIE init in FSP-S. Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in early pad configuration in bootblock also. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-28mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typoChris Wang
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mb/google/poppy/variants/nautilus: remove ALS for nautilusChris Wang
nautilus doesn't support ALS. remove the definition from ec.h. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Ib357328799015f78b18cd260db221e524e98cef7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mainboard/google/kahlee: Update Grunt for 16MB ROM chipMartin Roth
- Update Grunt to 16MB chip in Kconfig. - Move chromeos.fmd into variant directory & update Kconfig with the new location. - Add Grunt specific chromeos.fmd file. BUG=b:69691210 TEST=Build grunt; Build & Boot Kahlee Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28mainboard/google/kahlee: Update chromeos.fmdMartin Roth
- Remove SI_ALL section. This is no longer needed as the PSP dirctory is placed into the RO coreboot section. - Add 1MB Legacy section. - Add Memory cache section. These sections are called "MRC", which is an Intel term, but AMD platforms will use the same regions for saving the same sort of data. BUG=b:65497959, b:67035984 TEST=Build & boot kahlee Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-27google/fizz: correct memory rcomp settingsKane Chen
Follow the schematic and Doc 573387 to correct the rcomp and rcomp target settings for fizz TEST= boot ok and the system can enter and resume from S3. Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Remove tpm i2c configs from KconfigShelley Chen
We are disabling tpm over i2c, so the configs are not needed anymore. BUG=b:65056998 BRANCH=None TEST=emerge fizz and make sure can still boot up. Change-Id: Id88f32fa952801749544534442fc15d85fc1a892 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Disable unused i2c linesShelley Chen
As cr50 has now switched to using SPI, no need to enable the i2c1 anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and I2C3. BUG=b:69374421 BRANCH=None TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many) reboots. cat /proc/interrupts. Make sure # interrupts for 16 after booting is reasonable (not > 10k) and idma64.0, i2c_designware.0 are not listed with that interrupt line anymore. Should look something like this: 16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23google mainboards: select SYSTEM_TYPE_LAPTOP where appropriateMatt DeVillier
Some Google boards are missing this selection, leading them to being incorrectly identified as type 'Desktop' in SMBIOS type 3 table. Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards' Kconfigs. TEST: boot Linux and check correct chassis type listed via dmidecode Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23sb/intel/i82801ix: fetch initial timestamp in bootblockArthur Heymans
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 18:56:37 +0000