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2020-01-10mb/msi/ms7707/devicetree.cb: Align contentsAngel Pons
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/wtm2/devicetree.cb: Align commentsAngel Pons
Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/emeraldlake2/devicetree.cb: Align contentsAngel Pons
Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/dg43gt: Make devicetree prettierAngel Pons
Use lowercase for hex constants and align comments and register values. Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/intel/dcp847ske: Make devicetree prettierAngel Pons
Align contents and fix some redundant comments. Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/foxconn/d41s/devicetree.cb: Indent with tabsAngel Pons
As on most other boards, use tabs to indent the devicetree. Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/compulab/intense_pc: Reformat devicetreeAngel Pons
Use subsystemid inheritance, which results in a much more compact devicetree. In addition, align and correct various comments. Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/compulab/intense_pc: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Iaa557b18c34584dccb5c889ab8bd2173ed4ea04b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/roda/rk886ex/devicetree.cb: Align commentsAngel Pons
Change-Id: I67e3149657c04f72aac0b20bc31af338129a13b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5ql-em/devicetree.cb: Do minor fixesAngel Pons
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8z77-m_pro: Make devicetree prettierAngel Pons
Align comments, and make PCIe port comments consistent. Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode. Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants and align some comments. Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants, inline a lone `end` and align a comment. Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro: Make devicetree prettierAngel Pons
Replace a bunch of spaces with tabs, put host bridge and friends above southbridge, fix "TPM Module" (Trusted Platform Module Module) and add some empty lines to help the reader. Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/veyron/devicetree.cb: Drop illogical commentAngel Pons
This comment seems to have been copied off some QEMU board. As it would not apply to any veyron variant, drop it. Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/nyan/devicetree.cb: Correct some commentsAngel Pons
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few minor typos. Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-09src/mainboard: remove MMIO macrosIdwer Vollering
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09AGESA,binaryPI boards: Declare some IRQ tables staticKyösti Mälkki
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B optionAaron Durbin
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer being used in the code. There's a runtime check for supporting fast read dual output mode of the spi flash. Remove the references to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B. Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08mb/google/hatch: Remove fixed IccMax valuesJamie Chen
Remove fixed IccMax values for all domains. IccMax will be selected by CPU SKU in fill_vr_domain_config function. BUG=b:145094963 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-07src/mainboard: Fix typoElyes HAOUAS
Change-Id: I8a486ce12d6a5f6de31afd279612dc37d3fffd83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-07mb/google/kahlee/treeya: Tune VIH and meet specPeichao Wang
According to vendor Bayhub requirement need tune VIH make it meets spec --0x304(6:4) CLK = 3 --0x304(3:0) DAT = 5 BUG=None TEST=build firmware and measure VIH whether meets spec Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I4de9e6cfb37e3b76f7afc206cbe3396b8da2d6dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37458 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07mb/google/kahlee/treeya: tune eDP delay time to 20 msPeichao Wang
tune eDP delay time to 20 ms ensure satisfy panel spec BUG=b:147270512 TEST=verify panel sequences by ODM. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06mb/*/*: Remove unused option_table.h includesKyösti Mälkki
These should have been removed together with read_option(). Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-05mb/sapphire/pureplatinumh61: Make devicetree prettierAngel Pons
Align contents, and fix some redundant comments. Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/gigabyte/ga-b75m-d3h: Align devicetree linesAngel Pons
Aligned text is easier to read. Change-Id: I66a8efec3587649746bd56cd17eac2a06c9cc500 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabsAngel Pons
As on most other boards, use tabs to indent the devicetree. Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-03mainboard/google/puff: Clean up KconfigEdward O'Callaghan
Let the linker trim unused net driver symbols when unused in devicetree rather than being overly zealous in the Kconfig. BUG=b:146592075,146999042,146999043 BRANCH=none TEST=Boot to kernel. Ensure we have ip address and corresponding mac address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: Ie98d0f9f9b77cb9ee4e52f6c95b68bcbdd94f2cc Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-01-03mainboard/google/puff: Clean up pcie 15.3 ep in dtEdward O'Callaghan
Clean up devicetree as nothing special is needed here. BUG=b:142769041 BRANCH=none TEST=builds Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-01-02mb/**/acpi_tables.c: Drop lid settings on desktopsAngel Pons
Unlike laptops and some trash cans, desktop boards do not have a lid. Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-02asus/am1i-a: remove unnecessary VGA_BIOS_ID defaultMike Banon
The majority of Socket AM1 APUs [1] - three out of five - have the integrated VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here. [1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC) Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-02mb/ibase/mb899: Remove unused includesElyes HAOUAS
Change-Id: I496da344cc0d3845c308bca4d5da46d9ca6f88a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-02mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS
Change-Id: Ie8b9df7a64b45167de542182f3dfe6b320b9f2e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02mb/intel/d945gclf: Remove unused includeElyes HAOUAS
Change-Id: I023ce20b4144d782f22243911f845f6e28fdb2a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-02mb/google/beltino/**/hda_verb.c: Correct pin configsAngel Pons
NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead applied onto NID 0x1a. Fix that, so that it matches original Chromium sources for the boards. Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/google/beltino/**/hda_verb.c: remove preprocessor guardsAngel Pons
These files are not headers. Change-Id: Ibe6c9a96c1c4b0952a8d03b7a8b17869a66511f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/**/hda_verb.c: Correct codec ID on subvendor verbsAngel Pons
Looks like the subvendor verb for codec #3 is erroneously using zero as its codec number. Fix that. Change-Id: I760533c229287627dd0548a06300c376e045302c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/**/hda_verb.{c,h}: use denary numerals for codec IDsAngel Pons
Denary, also known as "decimal" or "base 10," is the standard number system used around the world. Therefore, make use of it. Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/ti/beaglebone: Remove unused includesElyes HAOUAS
Change-Id: Ifd1096cdf3700fa24ad8e5a701f48803650767bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-02Replace last uses of read_option() with get_option()Kyösti Mälkki
Change-Id: I63e80953195a6c524392da42b268efe3012ed41b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37953 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02mb/intel/jasperlake_rvp: Add initial mainboard codeAamir Bohra
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Jasperlake". 2. Replace "icelake_rvp" with "jasperlake_rvp". 3. Rename "icl" with "jsl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake" as tigerlake SOC hosts jasperlake code as well. 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC 10. Replace icl_u and icl_y variant with jslrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per jasperlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 10MB BIOS region. TEST=Build jasperlake rvp board Change-Id: I3314215807959b7348b71933fbba98e6487c0632 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-25 04:41:45 +0000