summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2018-06-21mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5Seunghwan Kim
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage. BUG=None BRANCH=poppy TEST=Verified the leakage is gone after update coreboot Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKUSeunghwan Kim
For supporting new SKU, we need to override GPIO table and device configuration. The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it. BUG=b:80052672 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27147 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-20aopen/dxplplusu: Add romstage timestampsKyösti Mälkki
Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-20mb/google/octopus: Configure EC_IN_RW correctlyFurquan Shaikh
This change fixes the following issues with EC_IN_RW signal: 1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in GPIO table for baseboard and bip. 2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can re-sample the GPIO at runtime. BUG=b:110084012 TEST=Verified that EC_IN_RW signal is read correctly in depthcharge. Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-06-20mb/google/octopus: Enable Synaptics touchpad devicewuxy
This change adds Synaptics device to phaser project. BUG=b:110236590 TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT,make sure the Synaptics Touchpad can work. Change-Id: Icc1e8c35a9de54ed04187fcf219a72a592d3bd81 Signed-off-by: Xingyu <wuxy@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27159 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18mb/google/poppy/variants/nautilus: Correct USB OC pin configurationSeunghwan Kim
Due to schematic, we need to correct USB OC pin configuration. - OC0 for Type-C Port 1 - OC1 for Type-C Port 0 - OC2 for Type-A Port - OC3 to NC BUG=NONE BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-18mb/google/octopus: Enable Synaptics touchscreen deviceFurquan Shaikh
This change adds ACPI properties for SYTS7817 device. BUG=b:110013532 Change-Id: Ifdec4efce169c066f212a393df21089d43d8e4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-18mb/google/octopus: Create fleex variantJustin TerAvest
This creates a fleex variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:110085182 TEST=None Change-Id: Ia8b8bb757f67bea997b7f43489c38cac62f7682d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27105 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17mb/pcengines: Remove unneeded includes and dead codeElyes HAOUAS
Fix coding style. Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-15mainboard/google/Kahlee: All variants identify as Grunt in SMBIOSMartin Roth
All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mb/google/poppy/variants/nami: Update DPTF table from version 1.5John Su
Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/kahlee: Enable keyboard backlight for careena specific SKUKevin Chiu
Enable keyboard backlight by Careena SKUID Set to 10% as the same as google/snappy project BUG=b:110065836 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14mb/lenovo/x200: Enable libgfxinitArthur Heymans
Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27013 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14mb/*/*: Enable libgfxinit on x4x boardsArthur Heymans
TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and HDMI2. Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_E2 for BT_DISABLE_LNick Vaccaro
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an output and initialize it high (high = out of reset). BUG=b:80089559 BRANCH=none TEST=none Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-14mb/google/poppy/variants/nocturne: config GPP_B4 for FCAM_PWR_ENNick Vaccaro
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of GPP_D8 as it needs a 3.3v gpio to provide enough power to also directly power the camera LED. BUG=b:79667559,b:78122599 BRANCH=none TEST=none Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-13src/mainboard/*: Remove empty vendor foldersAngel Pons
After removing most geode_lx boards, some mainboard directories are left empty. This patch cleans them up. Change-Id: I2e99eba3d49dec90ceb2ce0c7f61612a9840ce59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27092 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-11google/kukui: Add MediaTek MT8183 reference boardTristan Shieh
BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/*/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11google/fizz: fix LAN driver chip_info attachmentMatt DeVillier
As a result of commit: [711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device fizz's chip_info for the LAN driver is being overwritten/nulled, as the LAN device is on function 2 (PCIe port 3), but the driver info was set for the post-swapped PCIe port (1). Move the driver chip_info to function 2/port 3, so that it follows the PCI device function when swapped after FSP-s, and is correctly passed to the LAN driver. Test: boot google/fizz (teemo variant), check cbmem console and verify ethernet MAC address and LED config correctly set. Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11mainboard/google/kahlee: Remove unused baseboard codeMartin Roth
This code is no longer needed. BUG=b:107537694 TEST=Build & boot on grunt Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/eve: add vendor to subsystem idMatt Delco
The initial subsystem ID had a device ID but not a vendor ID. This change adds the Google vendor ID to the subsystem ID. Change-Id: I14897da115fd6f2ddd492b6c565bd23227197232 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/26987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-11mb/google/poppy/variants/nami: Add EC_ENABLE_TBMC_DEVICEShelley Chen
Add tablet motion control config to nami devices. BUG=None BRANCH=None TEST=run evtest make sure tablet switch value is 1 in tablet mode and 0 when not in tablet mode Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26970 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/google/poppy/variants/nocturne: enable nvmeNick Vaccaro
- configure GPP_B7 (PCIE_NVME_CLKREQ_ODL) for NF1 - enable root port 9 - add nvme register settings to devicetree BUG=b:78122599 BRANCH=chromeos-2016.05 TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage', boot to kernel, and verify /dev/nvme* entries exist. CQ-DEPEND=CL:1090070 Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11Fizz: Remove BJ adapter configurationDaisuke Nojiri
This patch removes BJ adapter configuration, which has been moved to the EC. BUG=b:109762580 CQ-DEPEND=CL:1089328 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I3041b984e7f02624b94ba2713b084d001fa155f9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/26965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mainboard/google/kahlee: Use 66MHz SPI clock for fast readMartin Roth
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/octopus: Fix GPIO to GPE mappings in devicetreeFurquan Shaikh
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus variants) changed the GPE mappings to accomodate for WiFi wake pin. However, this resulted in TPM interrupt pin being removed from the GPIO to GPE mapping. Since we do not support true interrupts in coreboot, GPE_STS registers are used to identify if an interrupt has triggered. Change in GPE mapping resulted in this information to be lost when talking to TPM thus resulting in "Timeout wait for tpm irq". This change fixes the above issue by assigning GPIO block for TPM interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to DW3. DW3 was mapped to NW_31_0 which only has debug header pins and CNVI pins (none of them are used for reading GPE_STS or as wake sources). BUG=b:109824918 TEST=Verified that there are no "Timeout wait for tpm irq" messages when talking to TPM. Change-Id: I30768177a838a684948f7485d760c8b83c3190f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-06-07mb/google/poppy: Select right TPM interfaceNaresh G Solanki
TPM over SPI/I2C config selection got changed in https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the same. BUG=None BRANCH=None TEST=Build for Soraka & make sure that TPM is probed over I2C interface rather than SPI. Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26890 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for SonaAmanda Huang
Since there are two cameras on Nami and only one camera on Sona. We need to disable rear camera/DMIC on all Sona sku. BUG=b:109710674 BRANCH=master TEST=Verify if only front camera/DMIC shown on Sona Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for PantheonAmanda Huang
Since there are two cameras on Nami and only one camera on Pantheon. We need to disable rear camera/DMIC on all Pantheon sku. BUG=b:109720689 BRANCH=master TEST=Verify if only front camera/DMIC shown on Pantheon Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/google/octopus: Update GPIOs as per latest schematicsFurquan Shaikh
Update GPIOs in baseboard to match latest schematics: 1. Get rid of STEST GPIOs(GPIO_{62,84-89}) 2. Get rid of SD_CD_ODL(GPIO_134) 3. Get rid of KB control GPIOs(GPIO_{144-146}) 4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the configuration for other pen GPIOs. BUG=b:109764138 Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26874 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06mb/*/*: Add a few VBT filesArthur Heymans
These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06drivers/intel/gma: Include mainboard data.vbtArthur Heymans
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path to point to the mainboard dir and to select INTEL_GMA_ADD_VBT_DATA_FILE by default. Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06mb/lenovo: Add ThinkPad W530 supportEvgeny Zinoviev
Tested and working: - Wi-Fi - Ethernet - WWAN ? (interface is created in linux, didn't actually test it, should work) - Bluetooth - Speakers - Internal mic - SD card reader - Suspend and resume - Keyboard, touchpad, trackpoint - Fan - Webcam - 4 RAM slots - All USB ports - mSATA - VGA ROM (FIXME: black screen after resume from s3) - Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3) - libgfxinit - GRUB payload - SeaBIOS payload - Internal flashing using flashrom Not tested yet: - Fingerprint reader - Colorimeter - Smart card reader - Docking station - VGA output - Optical disc drive - Discrete graphics TODO: - Test BDC detection Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/26136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-06hp/compaq_8200_elite: Fix TPM not visible in OSPatrick Rudolph
Chip sections must be covered by a PCI device. Fixes chip_ops not being executed and TPM shows up in OS. Change-Id: Id0ecd2f2f3e303f2228743369a8025b327bee61d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06mb/google/octopus: Fix invalid IOSSTATE settings for 1.8V pinsShamile Khan
When the normal termination is None, the standby termination is none also as per Doc# 572688. So when termination is only needed in standby, use the IOSSTATE setting that drives low/high via the Tx mode instead. Also disabled Speaker in Standby state to save power. BUG=b:79874891, b:79982669 BRANCH=None TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles pass. Checked that bluetooth is functional on resume. On Yorp, checked that speaker is functional after a suspend/resume cycle. Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 23:14:39 +0000