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2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12mb/google/octopus/variants/fleex: Set up tcc offset for fleexJohn Su
Change tcc offset from 0 to 10 for fleex. Refer to b:117789732#1 BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-11mb/emulation/qemu-i440fx|q35: Link memory.cPatrick Rudolph
Link memory.c instead of including it. Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-10mb/lenovo/t400: Improve docking codePatrick Rudolph
* Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-09mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 msChris Wang
Add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM. Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29473 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-09mb/google/kahlee: Tune eDP panel initialization timeChris Wang
1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-09mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/sarien: Disable eSPI when ACPI is enabledDuncan Laurie
Select the option to disable eSPI when ACPI is enabled so the EC is unable to assert an SMI when booted into the OS. There is a kernel driver that implements the same mailbox interface so it cannot also be used by the SMI handler. Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRSTNick Vaccaro
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29538 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11Nick Vaccaro
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead. BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2 Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/octopus/variants/baseboard: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I41b8268c752573d828e31a1d94d3f175aa3cc145 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29485 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08mb/google/poppy/variants/nami: add the hynix memory partsRen Kuo
add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2Michał Żygowski
This change allows to redirect coreboot console output to COM2 by setting appropriate UART index in Console menu in Kconfig. Change is helpful for users which would like to use COM1 port for other purposes, because COM1 is the only port with hardware flow control. Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/29255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl4 mainboard will follow in separate commits. Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07mb/{lenovo/x201,packardbell/ms2290}/romstage: Fix commentsPeter Lemenkov
RCBA address numbers in comments looks wrong and confusing. Let's fix them. This is a cosmetic change since no actual data is added or removed. Change-Id: I0e521acdac17959586bc0af7d8a2f7182f1e6721 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07mb/lenovo/*/*: Fix non-local header treated as localPeter Lemenkov
See also commit 4ad1446b with Change-Id I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated as local"). Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29501 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/lenovo/x201: Remove unnecessary include - delay.hPeter Lemenkov
Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-07mb/lenovo/x201/gpio: Use reset structurePeter Lemenkov
This structure was defined but never used. Let's use it. Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
Disable I2C7 because there is no device connected. Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07mb/google/sarien: Add sku_id functionDuncan Laurie
This change adds a sku_id() function that returns a static value to differentiate the sarien and arcada boards. Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/google/fizz: Comment variant names in KconfigDavid Wu
Refer to CL:1043916 BUG=none BRANCH=none TEST=none Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/poppy/variants/nami: Enable FP MCUShelley Chen
Some variants of nami will have a fingerprint MCU. BUG=b:118503113 BRANCH=Nami TEST=None (build and boot, but no hw yet) Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/asus/p5qc: Fix spelling of MarvellJonathan Neuschäfer
Marvell is the chip company, Marvel makes comic books. Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/29347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-05mb/google/sarien: Enable WWAN detectionLijian Zhao
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-05mb/google/fizz: Remove variant_cros_gpios from variantDavid Wu
This change removes the function defintions from variant so that the weak definition in baseboard can be used. Refer to CL:813944. BUG=none BRANCH=master TEST=Build and boot on DUT Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/fizz/variants/karma: Update GPIO GPP_D9David Wu
Update GPP_D9 to fix audio jack can't detect issue. BUG=b:118393646 BRANCH=master TEST=Verify audio jack can auto detect. Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/octopus/var/bobba: Define GPIO_134 as EC_SYNC_IRQEnrico Granata
Use GPIO_134 as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. BRANCH=none BUG=crbug:896347, b:118443377 CQ-DEPEND=CL:1298699 TEST=verify sensor events coming in on a reworked board with companion EC and kernel patches Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/29278 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05mb/google/poppy/variant/nocturne: add Nanya memory optionNick Vaccaro
Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05src: Remove unneeded include <arch/ioapic.h>Elyes HAOUAS
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05amd: Fix non-local header treated as localElyes HAOUAS
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05src/mainboard: Remove irrelevant conditional statementElyes HAOUAS
Using a conditional statement to return 0 or 1 depending on a logic value is unnecessarily complex. Change-Id: I449ce2b71b72374de5ec4986f9cc9f91a67856ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29265 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-04src/mb/asus/p5qc: Fix some mistakesAngel Pons
There are some small mistakes in these recently-added mainboards: - board_info.txt: Lists board socket incorrectly. - cmos.default: Loglevel was decreased some time ago. - devicetree.cb: Spelling mistake. - Kconfig: Mainboard name does not have a hyphen. Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-02google/kukui: Add board id supportTristan Shieh
Get board id from AUXIN4 and RAM code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02mb/google/sarien: Enable Wilco ECDuncan Laurie
The Sarien mainboard uses the newly added Wilco EC. - enable CONFIG_EC_GOOGLE_WILCO - add the device and host command ranges to the devicetree - have the mainboard SMI handlers call the EC handlers - add EC and SuperIO devices to the ACPI DSDT - call the early init hook for serial setup Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02mb/google/sarien: Add Arcada variantDuncan Laurie
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02mb/google/poppy/variants/nami: Enable radium touchscreen supportRen Kuo
Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mainboard/intel/icelake_rvp: Add ICL flash layout to support IFWI 1.6Aamir Bohra
Modify flash layout to match ICL-IFWI layout for early SoC PO support Flash Reg 0: Descriptor [0x0 - 0xFFF] Flash Reg 1: BIOS [0x400000 - 0xFFFFFF] Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW) [0x81000 - 0x3FFFFF] Flash Reg 8: EC (applicable for Intel RVP with internal EC support) [0x1000 - 0x80FFF] Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29316 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01sb/intel/common: Create a common implementation of `acpi_fill_madt()`Tristan Corrick
The function `acpi_fill_madt()` is identical among all the Lynx Point boards and sb/intel/bd82x6x, so share a common function between them. Earlier Intel platforms have similar implementations of this function. The common implementation might only need minor alterations to support them. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/lynxpoint: Add a common platform.asl fileTristan Corrick
The platform.asl file is copied from sb/intel/bd82x6x, and also matches the contents deleted from each mainboard's platform.asl. Tested on an ASRock H81M-HDS and a Google Peppy board (variant of Slippy). No issues arose from this patch. Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 00:22:07 +0000