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2013-05-07asrock/e350m1: reduce default stack sizeStefan Reinauer
The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes Removing the Kconfig variable STACK_SIZE to use the default results in the following numbers of stack usage. $ grep stack coreboot_with_patch.log CPU1: stack_base 00287000, stack_end 00287ff8 CPU1: stack: 00287000 - 00288000, lowest used address 00287da8, stack used: 600 bytes CPU0: stack: 00288000 - 00289000, lowest used address 0028875c, stack used: 2212 bytes [1] http://review.coreboot.org/#/c/3154/ (comment May 2 10:21 AM) Change-Id: Ibdb2102c86094fce3787e3b5a162ca8423de205c Signed-off-by: Stefan Reinauer <reinauer@google.com> Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3209 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-06exynos5250/snow: deprecate time.hDavid Hendricks
This re-introduces 2fde966 (http://review.coreboot.org/#/c/3177/) which was reverted due to unsatisfied dependencies. time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Change-Id: I8e60105629d9da68ed622e89209b3ef6c8e2445b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3201 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-04Lenovo ThinkPad X60: Clean up `romstage.c`Paul Menzel
1. Move comment for console init to correct place. 2. Start output with capital letter and add full stop at the end. 3. Add missing »)« at the end of description of GPIO 10. 4. Use tabulators instead of spaces. 5. Indent the code automatically using GNU indent [1] with the `-sc` switch adding stars in front of comment blocks as the good indent manual documents. $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c Leave the numbers left aligned as it is more beneficial to be able to run indent without adapting the result afterward. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3185 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-04Revert "exynos5250/snow: deprecate time.h"David Hendricks
This reverts commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04 Somehow this got merged before its dependencies. 3190 must be merged first, followed by 3176. However 3190 will fail while this patch is in. So the situation can't correct itself. Reverting this until the other two go in. Change-Id: I176f37c12711849c96f1889eacad38c00a8142c4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3195 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-04Asus F2A85-M Enable the SD controller for F2A85-MRudolf Marek
If the SD controller is "off" hudson.c won't disable that because, there is no code for this yet. The PCI device is still visible and PCI BAR will be allocated by Linux. Unfortunately it may happen that the particular address is used by non-standard BAR for SPI controller. Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3167 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03exynos5250/snow: deprecate time.hDavid Hendricks
time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5 Reviewed-on: http://review.coreboot.org/3177 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPICDavid Hubbard
Stefan Reinauer suggested 'select UDELAY_LAPIC' did not belong in f2a85-m/Kconfig. It got there via copy-paste from thatcher/Kconfig so this commit removes the 'select UDELAY_LAPIC' from both and puts it in cpu/amd/agesa/family15tn/Kconfig Since f2a85-m is the only Thatcher board coreboot supports right now, this should not break any other boards. Change-Id: I811b579c31f8d259a237d3a6724ad3b17f3a6c3e Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-on: http://review.coreboot.org/3178 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-05-01AMD Hudson A55E: Remove GEC firmware blob kconfig promptBruce Griffith
The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3127 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-01Google/Snow: Revise bootblock initialization.Hung-Te Lin
It's fine to always start timer even in suspend/resume mode, so we can move the timer_start() back to the very beginning of boot procedure. That provides more precise boot time information. With that timer change, the wake up state test procedure can be simplified. Verified by building and booting firmware image on Google/Snow successfully, and then suspend-resume without problem (suspend_stress_test). Change-Id: I0d739650dbff4eb3a75acbbf1e4356f2569b487d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01Google/Snow: Remove duplicated SPI1 initialization in bootblock.Hung-Te Lin
The firmware media source (SPI1) is already initialized by Exynos iROM. There is no need to do it again. Verified by building and booting Google/Snow successfully. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30Google/Snow: Remove unnecessary serial console init code.Hung-Te Lin
The "console_init" does initialize UART driver (which will setup peripheral and pinmux) and print starting message. Duplicated initialization can be removed. Also, console_init (from console.c) is always linked to bootblock (and will do nothing if CONFIG_EARLY_CONSOLE is not defined) so it's safe to remove #ifdef. Verified by building and booting on Google/Snow, with and without CONFIG_EARLY_CONSOLE. Change-Id: I0c6b4d4eb1a4e81af0f65bcb032978dfb945c63d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3150 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.Denis 'GNUtoo' Carikli
Enable `EARLY_CBMEM_INIT` for CBMEM console support by looking how other boards do this. This commit is tested by enabling the CBMEM console (`CONSOLE_CBMEM` in Kconfig) and then in GRUB 2 (as a payload) with the cbmemc command from the cbmemc module and in userspace with ./cbmem -c. Both worked. Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3142 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-04-30Google/Snow: Temporary fix for resume failure.Hung-Te Lin
The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause resume to be unstable, especially when X is running. System may show X screen for few seconds, then crash randomly and unable to recover - although text console may still work for a while. Probably caused by corrupted memory pages. 'mem_reset' (which refers to RESET# in DDR3 spec) should be enabled according to DDR3 spec. But it seems that on Exynos 5, memory can be initialized without setting mem_reset for both normal boot and resume - at least no known failure cases are found yet. So this can be a temporary workaround. Verified by booting a Google/Snow device with X Window and ChromeOS, entering browser session with fancy web pages, closing LID to suspend for 5 seconds, then re-opening to resume. Suspend/resume worked as expected. Also tried the "suspend_stress_test" with X running and finished 100 iterations of suspend/resume test without failure. Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3148 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-29Google/Snow: Enable suspend/resume.Hung-Te Lin
Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-26google/snow: Revise romstage initialization code.Hung-Te Lin
Move board setup procedure to snow_setup_* functions, and Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3130 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-25google/snow: Add "wakeup" module for suspend/resume.Hung-Te Lin
The "wakeup" procedure will be shared by bootblock and romstage for different types of resume processes. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully building and booting Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3129 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25arm/exynos: Allow DRAM controller to be initialized without clearing RAM ↵Hung-Te Lin
content. To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23AMD Thatcher: ConnectorTypeDP supports both DP and HDMISiyuan Wang
It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3088 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23GOOGLE/SNOW: get graphics workingRonald G. Minnich
This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins)
2013-04-20AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`Paul Menzel
Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: disable unused USB3.0 PLL to save powerDavid Hendricks
This PLL is unused and can be disabled to save about 250mW. Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3109 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: Minor clean-ups for display setup code in ramstageDavid Hendricks
This just cleans up a few areas: - Removed an unnecessary delay from exynos_dp_bridge_setup() - The delay at the end of exynos_dp_bridge_init() is necessary, so removed the comment suggesting that it might not be. - Simplified exynos_dp_hotplug Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: enable clock gating to save powerDavid Hendricks
This enables clock gating to save power on unused IPs. Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3110 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMISiyuan Wang
This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1] I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. [1] http://review.coreboot.org/#/c/3088/ Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19[3/3] google/snow: enable TMUDavid Hendricks
This enables the thermal management unit (TMU) on Snow. Change-Id: Idd76af40bf0a5408baf61ef2665fd52ae4e260ba Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3108 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-18AMD Fam14: Split out the AMD Fam14 DSDTMike Loptien
Same splitting as done on Persimmon and ASRock. Moving common DSDT code to common areas and adding new files as necessary. Boards updated are: Inagua Union-Station South-Station Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17google/snow: enable 32KHz sleep clockDavid Hendricks
Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3075 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16AMD Parmer: remove unused macros and turn off unused pcie portSiyuan Wang
1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1]. 2) Disable unused PCIE port in devicetree.cb. PCIE port 3 is not used in Parmer. This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2]. [1] http://review.coreboot.org/#/c/3087/ [2] http://review.coreboot.org/#/c/3011/ Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3099 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16snow: Return 0 from get_recovery_mode_from_vbnv.Gabe Black
This function isn't yet used for much, or perhaps anything, but where it appears in the code it's ored with other values. Since we're not actually retrieving anything, it might be best to return 0 so that the other values that are being ored in can be expressed and this function can stay dormant until it actually has something to do. Change-Id: I6edc222a5c2d00ece2ecfad5191a615331eeaf16 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3098 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-04-16snow: Report the state of the power button GPIO in the coreboot tables.Gabe Black
Change-Id: Ia7ce2b7342e186c565b92211e3ac15d80ce24b38 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3097 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Configure the power button as an input GPIO.Gabe Black
We need to read it to report its value to the payload. The kernel will reconfigure it as an external interrupt, but we'll make it a regular input for now. Change-Id: I019bd2c2731144d3b7bb53fad0c2c903874f616c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3096 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-16snow: Fix the name of some constants in romstage.c.Gabe Black
These names were inherited from chromeos.c where they've already been fixed. Change-Id: I7ad57b979b7b8f42f6bd68d1ecf887caba3fa3f1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3095 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Get rid of the oprom loaded GPIO.Gabe Black
ARM doesn't use option ROMs, so this value doesn't make sense. Change-Id: I1a0f0854e1dd4b9594ca0c147e590337520436da Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3094 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Tidy up chromeos.c.Gabe Black
Got rid of a lot of #defines, some of which were converted to enums and the rest which were eliminated entirely. Got rid of cruft in get_developer_mode_switch and started using it for the dev mode GPIO. Instead of a macro defining how many GPIOs are expected, now the code actually counts the GPIOs as they're added. Change-Id: I97b6b9f52a72d1276eb3cf36d7f9dd7b335b4d19 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3093 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Add support for EC based recovery.Gabe Black
Implement the get_recovery_mode_switch function using the newly added I2C based Chrome EC support. Change-Id: I9d0200629887f202edf017cba3222a7d7f5b053e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3092 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Fix some comments in chromeos.c.Gabe Black
The comment about the lid switch was left over from when this file was copied from another board and was incorrect. Also fixed a capitalization inconsistency. Change-Id: Icefd19047971e13c08f615578e4a181e82a2997f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3091 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16Lenovo ThinkPad X60: Add Native VGA init.Denis 'GNUtoo' Carikli
The code has been taken from the google link mainboard and modified to fit the ThinkPad X60. Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/2998 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16ec/google: Support Google's Chrome EC on I2C interface.Hung-Te Lin
Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3074 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES againKyösti Mälkki
These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES« (1c5071d1) [1] but were unfortunately introduced again in new ports. [1] http://review.coreboot.org/1414 Change-Id: I5eb61628141aefd08779615702d51ca155fa632a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2707 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-14link/graphics: Remove the inclusion of an AMD header.Denis 'GNUtoo' Carikli
link(google chromebook pixel) is an intel machine. Change-Id: I9d40f1e945021d8e190879477cd12be7d0262733 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3085 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-13exynos5/snow: remove wait_ms arg from dp_controller_init()David Hendricks
This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3078 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-13Exynos5250: add a microsecond timerRonald G. Minnich
Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3073 Tested-by: build bot (Jenkins)
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5: commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5 Author: Patrick Georgi <patrick.georgi@secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> It sneaked in without it's dependencies and, therefore, broke the build for all amdk8 targets. Paul Menzel already commented on the issue in [1]. It also doesn't look like the dependencies would be pulled soon [2]. [1] http://review.coreboot.org/#/c/3047/ [2] http://review.coreboot.org/#/c/2662/ Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3063 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-12AMD Thatcher: Fix PCIE link issuesSiyuan Wang
1). Thatcher PCIE x8 slot is reverse order. Although the PCIE slot is x16, it actually uses 8 lanes(15:8). Because the PCIE slot is configured by PortList[0], fix this item can enable the slot. A x1 PCIE network adapter works well in this slot. 2). Fix DdiList to detect DP monitor or HDMI monitor. GPIO50 can be used to detect DP0/HDMI0 monitor. If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor. GPIO51 can be used to detect DP1/HDMI1 in the same way. 3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb. PCIE port 3 and 7 are not used in Thatcher. Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3011 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.Gabe Black
We need these to be inputs so they can be read when populating the coreboot tables. It seems like a good idea to do this early to ensure that the input gate capacitance has had a chance to charge, and if we decide to use actually use that information during the ROM stage to do earlier RW firmware selection. It is not guarded by a ChromeOS config variable because those lines are always intended to be input GPIOs, regardless of whether we're running ChromeOS or not. Change-Id: Id76008931b5081253737c6676980a1bdb476ac09 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3067 Tested-by: build bot (Jenkins)
2013-04-11Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number.Gabe Black
Change-Id: I34097f878291367b28962048190e11ccaacfc514 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3066 Tested-by: build bot (Jenkins)
2013-04-11ASRock DSDT: Split the ASRock DSDTMike Loptien
This is the same split as was done on the Persimmon. Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3050 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10GOOGLE/SNOW: add edp support to ramstageRonald G. Minnich
Add basic edp support to the ramstage. Not working. Change-Id: I15086e03417edca7426c214e67b51719d8ed9341 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3055 Tested-by: build bot (Jenkins)
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