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2017-08-10nb/intel/sandybridge/raminit: Add Kconfig option for fusesPatrick Rudolph
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
2017-08-10mb/lenovo/t*00/romstage: Switch to new hybrid driverPatrick Rudolph
Get rid of old hybrid graphics driver and use the new one. 1. Disable IGD and PEG in early romstage. The PEG port will get disabled on devices that do not have a discrete GPU. The power savings are around ~1Watt. The disabled IGD does no longer waste GFX stolen memory. 2. Get rid of PCI driver The Nvidia GPU can be handled by the generic PCI driver and allows to use the ACPI _ROM generator for Switchable graphics. 3. Settings are stored in devicetree. One driver for all Lenovo hybrid graphics capable devices. 4. Add support for Thinker1 GPU power handling. Only boards that do use reference design 2012 are known to be supported. Needs test on boards that do you use reference design 2013. Should reduce idle power consumption when using IGD by ~5Watt. Tested on Lenovo T430 without DGPU. PEG port is disabled. Needs test on all devices. Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-10mb/lenovo/t400: Switch to new hybrid graphics driverPatrick Rudolph
Use new hybrid graphics driver to get device state. Move remaining code to romstage.c. Tested on Lenovo T500: * Linux 4.11.4 on Fedora 25 * Integrated (using NGI) * Discrete (using VGA OpROM) * Switchable (using NGI and VGA OpROM), tested with DRI_PRIME No regressions found. Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-10mb/intel/dg43gt: Add mainboardArthur Heymans
This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA with AHCI * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * VGA (on DVI) with NGI if patched to use DVI gmbus port for output * PCI * Reboot and S3 resume * Descriptor mode with ME disable straps and ME region absent (no working gbe in this configuration though) * USB. What does not work: * GBE (probably requires working ME); * Analog on DVI port out is shaking, which is not the case with vendor BIOS (setting clockgen on smbus 0x69 like vendor fixes it). * Booting with ME enabled (needs raminit patches for that) Not tested: * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10google/kahlee: Set eMMC slotMarc Jones
Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09intel/common/block/smm: Update smihandler to handle gpiBrandon Breitenstein
Updating the common smihandler to handler gpi events which originally were going to be left to each soc to handle. After some more analysis the gpi handler can also be commonized. Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09mb/lenovo/x1_carbon_gen1: add missing '+' in spd/MakefileAlexander Couzens
Each line of spd config overwriting the slot 0 instead of appending it. Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-on: lenovo x1 carbon gen 1 with elpida 8GB Fixes: e9787ff61f81 ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2") Reviewed-on: https://review.coreboot.org/20918 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-08mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2Nico Huber
Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-08-08mb/lenovo/l520/Kconfig: Remove hybrid graphics driver supportPatrick Rudolph
The schematics isn't available for the board, but other L*00 series boards seem to use a different, compared to T*00 series, GPIO layout. As it has never been tested, remove the broken driver. Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-08mb/intel/d510mo: Configure clockgenArthur Heymans
Configuring the clockgen like vendor bios fixes the issue where the display wobbles from left to right on the analog VGA output. Note: This seems to be common issue/requirement on Intel devices from that generation (also happens on dg43gt). TESTED on Intel D510MO. Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-04mainboard/google/poppy: Decrease link-frequencies for OV13858 and OV5670V Sowmya
Decrease the link-frequencies as recommended by Omnivision for OV13858 and OV5670 camera sensors. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2017-08-04mainboard/google/soraka: Configure GPP_B8 in bootblockFurquan Shaikh
GPP_B8 acts as input to the inverter whose output controls PERST# signal to wifi module. Out of reset, GPP_B8 is configured as input by default. Since there is no external pull-down on it, this line is floating and results in PERST# being asserted until ramstage where the GPIO was originally configured. Because of this the wifi chip is not ready during the PCIe initialization step. Move the configuration of GPP_B8 to bootblock so that wifi device is taken out of reset as early as possible. BUG=b:64181150,b:62726961 TEST=Verified with warm reboot and suspend-resume stress test that wifi is still functional. Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04mainboard/google/soraka: Add gpio.c to bootblockFurquan Shaikh
Add gpio.c to bootblock so that the variant early_gpio_table can be used for configuration in bootblock. BUG=b:64181150,b:62726961 Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define AGESA_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-01google/gru: Correct Scarlet pwm regulator minimum value and maximum valueLin Huang
In Scarlet pwm regulatoror minimum value and maximum value differs from other board variants, Correct it so we can get the right voltage. Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01google/gru: Correct the Sdcard control gpio setting for ScarletLin Huang
in Scarlet the Sdcard control gpio differs from other board variants, So set the GPIO to high on Scarlet. Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-01google/gru: Use 1.8V powerdomain for gpio4cd on ScarletLin Huang
Scarlet gpio4cd use 1.8V powerdomain, let's make a correct register setting, otherwise even the uart does not work. Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-31google/kahlee: Add mainboard GPIOs to ACPIMarc Jones
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Move mainboard_ec_init to chip init phaseMarc Jones
Move mainboard_ec_init out of mainboard enable to the more appropriate mainboard init phase. Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Add EC and GNVS ACPIMarc Jones
Add ACPI support for the Google EC, which requires GNVS support for passing information from the EC to firmware and OS. Change-Id: I0a308bcd608a135cc9633273a05527f020b60743 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Enable TPMMarc Jones
Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Save VBNV data to CMOSMarc Jones
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Set DDI port 2 to DPMarshall Dawson
Set DDI port 2 type to Display Port. Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Setup the I2S audio codecMarshall Dawson
Inform AGESA to setup an I2S codec instead of an Azalia codec. This is step one for audio to work. ASL to connect the driver and the hardware is in a follow-on patch. Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/19841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-30intel/sandybridge: Clean VGA BIOS ids up a littleNico Huber
Sync map_oprom_vendev() and autoport with the list of PCI ids in the `gma.c` driver, remove one obsolete Kconfig default override. Change-Id: I12f24f415b695c516fbb947114e09c873af2e439 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaultsNico Huber
All affected boards did the same USE_NATIVE_RAMINIT distinction or actually selected USE_NATIVE_RAMINIT. Also update autoport. Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20813 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-07-28google/kahlee: Add ASL for Elan touchpadIvy Jian
Add ASL for the Elan touchpad driver connection in ChromeOS. This is based on the Auron and Rambi ASL. The AMD ACPI code doesn't have the auto table generation the newer Intel Chrome SOC use. Device visible to OS: /sys/bus/acpi/devices/ELAN0000 Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Fix ASL whitespace and formattingMarc Jones
Clean up the ASL whitespace and formatting to match the iasl -d style as other parts of coreboot. Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Remove conflicting AAHB IRQ ASLIvy Jian
The AMD internal A-link (AAHB device) doesn't support an IRQ, so remove it. This solves a conflict with the GPIO IRQ required for touchpad operation. Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28mb/google/soraka: configure GPP_B8 to control WLAN_PE_RSTRizwan Qureshi
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8. Configure GPP_B8 to drive low. TEST=Wifi card is detected and connect to an AP. Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27google/kahlee: Set SERIRQ to continuous modeMarc Jones
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet. Set continuous mode until the quiet mode feature is available. This allows keyboard and other EC based interrupts through. Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19840 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Pass GPIO setting in amdinitenvMarshall Dawson
GPIOs for I2C3 were being unset in amdinitmid if the GPIO enable table wasn't passed. It had been initialy set in amdinitreset. Pull the GPIO settings into their own file that can be used in bootblock and later stages. Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update PCIe link/lane configurationMarshall Dawson
Enable: GPP0 x1 - WLan GPP1 x1 - Card Reader Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set FADT legacy and 8042 supportedMarc Jones
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly report in the FADT. Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19836 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Add ChromeOS and ChromeECMarshall Dawson
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update GPIO tableMarshall Dawson
Update GPIO settings based on the schematic. Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27google/kahlee: Update for single DIMMMarshall Dawson
Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Remove AMD IMCMarshall Dawson
Kahlee does not use the AMD IMC. Remove the files and calls. Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19832 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Update KconfigMarc Jones
Update for the Stoney Ridge FT4 package and the on chip UART. Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Start Kahlee mainboardMarc Jones
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27siemens/mc_apl1: Select skip RAPL configurationMario Scheithauer
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant power management of the processor package. An active RAPL algorithm leads to negative effects with our real time software. Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27mainboard/google/poppy: Configure GPIO.1 and GPIO.2 for daisy chain modeV Sowmya
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively for TPS68470 PMIC in daisy chain mode. * GPIO.1: Sensor SDA in daisy chain mode. * GPIO.2: Sensor SCL in daisy chain mode. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 07:25:51 +0000