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path: root/src/mainboard
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2016-01-26ga-g41m-es2l: Instead of forcing native VGA, make it selectableMartin Roth
This allows the native VGA to be disabled for debug, or if someone wants to use the vbios. Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12848 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-01-26mainboard/intel/d510mo: Licence fixes and azalia verb tableDamien Zammit
Azalia verb table replicated from vendor bios. Licence headers added where appropriate. Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12621 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-25mc_tcu3: Enable auto generated attributes in cbfsWerner Zeh
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position and alignment attributes in cbfs. Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13123 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-01-24purism/librem13: Fix select of EC_PURISM_LIBREMMartin Roth
This was misspelled as EC_PURISM_LIBEM, causing the EC to not get included in the build. Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13178 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-22google/oak: Configurate SD card detection pinYidi Lin
BRANCH=none BUG=chrome-os-partner:47609 TEST=remove servo board connection and insert/remove an empty SD card in recovery mode. Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6 Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313073 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
BRANCH=none BUG=none TEST=boot to kernel Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55 Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313969 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22lib: compile mdelay for romstagePatrick Georgi
Mimicking change I7037308d2, always compile mdelay for romstage. The boards that #included delay.c in the romstage now rely on the linker instead, which is a desirable cleanup. Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22google/oak: setup usb and configure I2C level shift pinBen Lok
BRANCH=none BUG=none TEST=build pass and verified on rev3 Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292689 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13096 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Configure backlight control pinsYH Huang
Since backlight is controlled in depthcharge, we only configure control pins as output pin and set them power-off in the coreboot stage. BRANCH=none BUG=none TEST=Saw DEV screen during boot process. Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754 Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292686 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13093 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13092 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Disable vboot mock data, now that I2C is functionalLiguo Zhang
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I7a635c57ba271c8f568bd3334929acdf6a058ce8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13078 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Enable MMU supportJimmy Huang
BRANCH=none BUG=none TEST=build pass [pg: split into multiple commits] Change-Id: I6e165cfa6a8345de3d8d5461a75d5ed626ece4ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13077 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Add support for verstageItamar
Add support for verstage [pg: split original commit into multiple commits] Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Enable SPI supportLeilk Liu
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I19f970db40fb8563ef1b782a9606ca3766ef2ac5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87 Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0 Original-Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292661 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22Cyan: Update DPTF parameters for higher temperatureT.H.Lin
TEST=Run DPTF CQ-DEPEND=CL:12729 Original-Reviewed-on: https://chromium-review.googlesource.com/295478 Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119 Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Reviewed-on: https://review.coreboot.org/12747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22purism/librem13: Add support for Purism Librem 13 mainboardDuncan Laurie
This adds support for booting the Purism Librem 13 mainboard with coreboot, using binaries extracted from the original BIOS and from a Broadwell Chromebook. The following features have been tested on Ubuntu 15.10: - Input: Keyboard and Trackpad - SATA: Internal HDD and M.2 NGFF - Network: WiFi and Ethernet - USB: Bluetooth, Camera, SD Card, Ports (1xUSB2 and 1xUSB3) - Video: Internal panel and HDMI port - Internal speakers and microphone (headphones do not work) - EC handling for battery, AC, lid, special keys These binaries are extracted from the original BIOS: - VGA BIOS - Management Engine - Intel Firmware Descriptor These binaries are extracted from a Broadwell Chromebook BIOS: - MemoryInit reference code binary - SiliconInit reference code binary This was developed and tested on an Librem 13 device. For those who may want to do more development you can use EHCI debug and the right USB port to get coreboot output. Change-Id: Ia72e2d7ddc8ba5eef63819e5677122a5a5c705d8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13026 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cbKane Chen
SVID config set to SVID_PMIC_CONFIG BUG=none BRANCH=none TEST=build, boot to OS and check the register is set properly Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308576 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13117 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/cyan: Add Wifi regulatory methodHannah Williams
WRDD method in wifi.asl returns the regulatory domain code. This value is read from VPD in wifi_regulatory_domain() and saved to global nvs if CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if CONFIG_HAVE_REGULATORY_DOMAIN is not enabled. Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13055 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/strago: Add method for Wifi regulatory domainHannah Williams
WRDD method in wifi.asl returns the regulatory domain code. This value is read from VPD in wifi_regulatory_domain() and saved to global nvs if CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if CONFIG_HAVE_REGULATORY_DOMAIN is not enabled. Original-Reviewed-on: https://chromium-review.googlesource.com/315131 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I52e0a052d31f36c6dc04e6a0953456350e7d86c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22skylake mainboards: Enable CONFIG_VBOOT_EC_SLOW_UPDATEDuncan Laurie
Updating EC+PD takes long enough to update that it is good to show the "critical update" screen when doing an EC/PD update. BUG=chrome-os-partner:49650 BRANCH=glados TEST=Build and boot on chell in normal mode with an EC update payload and ensure that it reboots to enable graphics, shows the "critical update" screen, and then reboots to disable graphics init again. Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configsDavid Hendricks
This is a follow-up to CL:320623 to make veyron DRAM configs uniform (except for Rialto). As discussed in chrome-os-partner:43626, the mr[3] value and ODT are set diffently for Mickey, thus the .inc files for other boards have mr[3] = 1 and ODT disabled. BUG=none BRANCH=veyron TEST=compile tested for veyron Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab Original-Reviewed-on: https://chromium-review.googlesource.com/321870 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13109 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21google/veyron_mickey: Update Hynix memory configurationLang Zhang
Update Hynix memory configuration for mickey so that it can boot on Hynix board. BUG=chrome-os-partner:48637 BRANCH=master TEST=Boot on mickey hynix board Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01 Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320623 Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com> Original-Tested-by: lang zhang <kingsley_zhang@asus.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21google/tidus: initial upstream migrationMatt DeVillier
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium tree to upstream, using google/guado as a baseline. TEST=built and booted tidus with full functionality Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-20Kconfig: Remove selects that enable 'choice' symbolsMartin Roth
Selecting Kconfig symbols that were created inside a 'choice' block have no effect. Remove these so people aren't confused by them. Change-Id: I7de9131d8d8afb65f86648afb9728f09cb67e122 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-19lenovo/t400: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I1e9732e178bb8422b284d80d9f3d34b72f2e2415 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19intel/kunimitsu: Add device properties for Nuvoton codecYong Zhi
This patch added default values for two SAR properies introduced by updated nau8825 codec driver. Also updated sar-threshold to improve button detection accuracy. Bug=chrome-os-partner:49394 BRANCH=glados TEST=Build for kunimitsu. Tested with 4-button headset Change-Id: I4096c60be54819d0ab2bf4b72a1e403f88d96af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b747e9dffed1c51131f0028879d4c22283c8ec5 Original-Change-Id: I3e222ff58c1483e261acf1cea297164966bf8689 Original-Signed-off-by: Yong Zhi <yong.zhi@intel.com> Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322241 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13014 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Adjust nuvoton 8825 button thresholds, add propertiesBenson Leung
Set "nuvoton,sar-threshold" property to thresholds based on tuning with the Android Wired Headphone Compatibility Kit and Chell EVT. Also set properties nuvoton,sar-compare-time and nuvoton,sar-sampling-time. The values of compare and sampling time align with the ones from this CL: https://chromium-review.googlesource.com/306372 Signed-off-by: Benson Leung <bleung@chromium.org> BUG=chrome-os-partner:49333 BRANCH=none TEST=Run evtest, selecting the input event for sklnau8825adi Using the Nominal headphones from the kit, check that the buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA", and code 582 (?) (should be voice search, but evtest doesn't understand) All of these buttons should work properly. Change-Id: I43dc1957f7d95744f41039a306d323806e66c56a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2bb545500afeb5b4fa0d1cd02dbf6453f19901ab Original-Change-Id: I126aae1e5ed1b9e1a2429e8c94fe08b3ba3ca736 Original-Reviewed-on: https://chromium-review.googlesource.com/322243 Original-Commit-Ready: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13013 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Modify DqsMapMike M Hsieh
Modify Dqs Byte Swizzling for channel 0 to honor chell's memory routing BUG=chrome-os-partner:48986 BRANCH=glados TEST=verified on chell system Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: Ic0485526bc1378e329c5eb0eeb57ff67a9501e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b60241e63381974655f5df5afcd913e95c17682b Original-Change-Id: I641502e8d303fa59e0f668d581745379e1ef4853 Original-Reviewed-on: https://chromium-review.googlesource.com/321524 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Add new memory part for DVT buildDuncan Laurie
After comparing datasheets it appears to have the same geometry and timings as the K4E6E304EE-EGCF part with just a new part number. BUG=chrome-os-partner:49357 BRANCH=glados TEST=build and boot on chell EVT (new part is not used until DVT) Change-Id: Ia1e67080b1d79600e00c3ea8bee088ecafea2ab2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb1488ca5ff780b5f1f937dbf0d23610c28204b2 Original-Change-Id: I09e1ce1a45a217afc88f422cf7db7924fad6b6f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321956 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-19intel/kunimitsu: Set I2C[4] port voltage to 1.8vNaresh G Solanki
As the audio card needs 1.8V I2C operation. This patch adds entry into devicetree.cb to set I2C port 4 operate at 1.8V. Branch=None Bug=chrome-os-partner:47821 Test=Built & booted kunimitsu board. Verified that I2C port 4 is operating at 1.8V level CQ-DEPEND=CL:*242225, CL:*241206, CL:315167 Change-Id: Ida69b885737aef0cfcf6a6ca21b3650169e614d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 990df9c1c65e75aae0a1329ead3790e78021b804 Original-Change-Id: Ifbb65e3d83561b52cc18e48b89d146c2f88f289b Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315168 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Set FSP params for min assertion widths and serirqDuncan Laurie
- Enable serial irq configuration in FSP. - Set minimum assertion width values for FSP to configure. - Set I2C4 voltage to 1.8V. - Enable SaGv feature to dynamically train memory frequency. BUG=chrome-os-partner:47688 BRANCH=none TEST=build and boot on chell EVT Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409 Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321212 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/glados: Set FSP params for min assertion widths and serirqDuncan Laurie
- Enable serial irq configuration in FSP. - Set minimum assertion width values for FSP to configure. - Set I2C4 voltage to 1.8V. - Enable SaGv feature to dynamically train memory frequency. - Disable Deep S3 to match chell so DeepSx story is consistent on skylake-y boards. BUG=chrome-os-partner:47688 BRANCH=none TEST=emerge-glados coreboot (tested on chell board) Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1 Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321211 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13008 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Reduce power-on keyboard backlight brightness to 25%Duncan Laurie
The keyboard backlight is very bright at 100% so be more subtle when turning it on at boot time. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on chell EVT Change-Id: I3925b94b4a455eb7d3bbb6eee414d21cf6d3bb93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 52da1456527bfa6e0a3290c87c4886e2b3111e21 Original-Change-Id: Ia3412b4052c96f5de8e8aef59f69f6b346b9aca8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321210 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/lars: Set Correct RCOMP Target for LARs EVT boardsSubrata Banik
Below are the correct RCOMP Target Values: Samsung K4E6E304EB part = {100, 40, 40, 21, 40} The rest of the DIMMs should have RCOMP set to {100, 40, 40, 23, 40} LARs EVT has new DIMM configurations, and the earlier RCOMP settings are not correct for the newly added DIMM cards, causing reboot issues. With this patch all the DIMMs get the required values programmed. BRANCH=None BUG=None TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS. No Reboot after this change. Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4 Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320527 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/lars: Enable eMMC HS400 modedavid
Kingston eMMC can now run under HS400 mode. BUG=chrome-os-partner:48017 BRANCH=none TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and MMC errors didn't happen. Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320194 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/13004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/chell: Enable eMMC HS400 modeRyan Lin
Hynix eMMC can now run under HS400 mode. BUG=chrome-os-partner:47647 TEST=run consective boot 100 times on Chell EVT Hynix SKU, and MMC errors didn't happen. BRANCH=none Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319627 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/lars: Enable SaGv featuredavid
This change enables SaGv feature for skylake platform. As a result of this patch the skylake platform will train memory at both low & high frequency points. This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled( SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Build and boot lars Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1 Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320022 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/13002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/kunimitsu: Enable FspSkipMpInit tokenRizwan Qureshi
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310192 Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45 Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312926 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12992 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243 Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319194 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13000 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in Lars with SkipMpInit enabled from CB CQ-DEPEND=CL:319353 Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12999 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Enable SaGv featureharidhar
This change enables SaGv feature for skylake platform.As a result of this patch the skylake platform will train memory at both low & high frequency points.This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled(SaGv disabled) 1=FixedLow(Fixed to low frequency) 2=FixedHigh(Fixed to High frequency) 3=Enabled(SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Tested on D1 silicon. Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651 Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315806 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12997 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: SPD changes for EVT boarddavid
Update Memory IDs for EVT board BUG=None BRANCH=lars TEST=Build and boot lars Change-Id: I8c0c731fc3a8eec0cb558137e9db90170debf2c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a95fbf063b2e41d551171228a1ea8cbcfdcaecc8 Original-Change-Id: I2be8a7db99f17ea2968d7e4c5de83cc3e4cbcd14 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319622 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP. FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5 Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319370 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12994 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Enable ALS connected to ECdavid
Lars has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I406b634176dac3f4cf1894e6b386af3306d11ffa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37d96458a11c33899f210cc04d3bdab07ec18746 Original-Change-Id: I017aeed1a8684676557e483ffa895dc4bb125d26 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319364 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Add keyboard backlight supportdavid
BRANCH=lars BUG=None TEST=alt+f6, alt+f7 Change-Id: I20d44ae806facf7470ab50d7b9ca4f36404b6ea3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bf8c26a11e632cc9f4112eace813478fb7ff8ca Original-Change-Id: Iaa59818f5d2d17eb6759cefa9b6fbfba82bb2fca Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/kunimitsu: Set BOOT_BEEP gpio to a default loRohit Ainapure
The BOOT_BEEP gpio is used to activate the buffer which isolates the I2S signals from PCH while doing a beep from depthcharge. It needs to be lo to deactivate the buffer for audio playback from OS. BUG=chrome-os-partner:47124 BRANCH=None TEST=boot depthcharge & test beep with devbeep. Boot OS and test audio playback. Change-Id: I047513f6cbe9590820dfe3c369161a157864be97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6 Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319220 Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Tested-by: Michael Rang <michael.rang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/chell: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted chell Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948 Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317870 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted glados Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317910 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12984 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 18:08:15 +0000