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2020-03-31mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESAMichał Żygowski
Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31drivers/intel/gma: fold gma.asl into default_brightness_levels.aslMatt DeVillier
Including gma.asl at the platform level (vs the board level) means that even desktop boards need to include the default brightness levels, which makes no sense. To begin to clean this up, include gma.asl in default_brightness_levels.asl (as well as the handful of board-specific brightness files) and remove it from the various platforms. A follow-on commit will remove default_brightness_levels.asl from all boards which lack an internal display. Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31mb/emulation/qemu-q35: Enable CHROMEOS as an optionDuncan Laurie
Allow Chrome OS to be enabled for this QEMU target. By default this does not change anything unless it is selected in the build configuration, but it makes it possible. Native VGA init is not forced when Chrome OS is enabled because the drm-bochs driver does not work with chrome (even the latest upstream kernel driver with drm atomic support) but it does work with virtio. The coreboot graphics init needs to match what is selected with qemu (with -vga std or -vga virtio) which in turn will determine which kernel driver is used. A second FMAP is added with both RW-A and RW-B regions which is required by chromeos. Recovery mode can be entered by supplying a custom fw_cfg option when launching qemu: -fw_cfg name=opt/cros/recovery,string=1 Change-Id: I24b4532ea961e68558663292c99d121f0a30ce3b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31mb/emulation/qemu-q35: Enable option for TPMDuncan Laurie
This enables the mainboard to use a TPM if it is selected in the configuration. By default this does nothing, but it allows the TPM to be enabled and used with the CONFIG_USER_TPM2 Kconfig option. Using a TPM with QEMU requires either a physical TPM backend or the swtpm package with a socket: -chardev socket,id=swtpm,path=/tmp/swtpm/socket -tpmdev emulator,id=tpm0,chardev=swtpm -device tpm-tis,tpmdev=tpm0 Change-Id: I0d79a5a0f590c57998ababb660b52d9e3ed2d484 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31mb/emulation/qemu-i440fx: Add acpi_name handler for QEMUDuncan Laurie
QEMU does not have a separate northbridge chip, so the mainboard needs to handle the ACPI name and paths so that devices can get generated into the SSDT properly. This fixes the PIRQ and TPM table generation. This issue can be seen in the coreboot output: ACPI_PIRQ_GEN: Missing LPCB ACPI path Change-Id: Ifc7d4359eea38ac0b55d655e39191ae7f8655fe4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31mb/emulation/qemu-i440fx: Reserve low memoryDuncan Laurie
Ensure that the low memory is properly reserved so it does not get marked as normal RAM and get wiped or reused by firmware or the kernel. This ensures that the low RSDP is always available for the kernel. This is only noticed if something wipes the RSDP before the kernel boots, which happens if you use the depthcharge payload and boot in developer mode. Change-Id: I7295018416229bc957ecbf26f77623a57965557e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31mb/emulation/qemu-q35: Increase max size of ACPI tablesDuncan Laurie
When the TPM is enabled in QEMU the fw_cfg interface will return ~200KiB of ACPI tables, so this needs to be increased from the default in order to be able to boot. This is seen when using a TPM with qemu as it will hang when processing the fw_cfg tables. qemu-system-x86_64 \ -machine q35 -enable-kvm -vga virtio -serial stdio \ -drive 'id=hd,file=disk.bin' -bios coreboot.rom \ -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \ -tpmdev 'emulator,id=tpm0,chardev=swtpm' \ -device 'tpm-tis,tpmdev=tpm0' Change-Id: I21980aace8e86e636f5ae7b55148f4c31404edba Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31mb/51nb/x210: restore left USB3 port in devicetreeMatt DeVillier
Was accidentially removed in 6e50849 Change-Id: I090b6bc8863d17412cb1e23ac816c39f479290c1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39937 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31mb/google/slippy: Convert variants to use override devicetreeMatt DeVillier
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31mb/google/link: Use GENERIC_SPD_BINMatt DeVillier
Clean up Link's mainboard dir by putting the SPD files in a spd subdirectory like all other/newer boards use, and selecting GENERIC_SPD_BIN to include them in the build. Test: build google/link and verify spd.bin unchanged Change-Id: I9c2f9f77dbdd6552c5ae1e7a0df2051b9b85badc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-31mb/google/link: use default GMA display profileMatt DeVillier
Link's DID data makes no sense, and ACPI backlight controls don't work as a result. Replace them with the default profile used by most/all other boards. Test: build/boot google/link, verify ACPI backlight controls functional Change-Id: Ia7cb3f10bd3c05ebaf414c17a8f94d2e9b40ae26 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-31security/vboot: Decouple measured boot from verified bootBill XIE
Currently, those who want to use measured boot implemented within vboot should enable verified boot first, along with sections such as GBB and RW slots defined with manually written fmd files, even if they do not actually want to verify anything. As discussed in CB:34977, measured boot should be decoupled from verified boot and make them two fully independent options. Crypto routines necessary for measurement could be reused, and TPM and CRTM init should be done somewhere other than vboot_logic_executed() if verified boot is not enabled. In this revision, only TCPA log is initialized during bootblock. Before TPM gets set up, digests are not measured into tpm immediately, but cached in TCPA log, and measured into determined PCRs right after TPM is up. This change allows those who do not want to use the verified boot scheme implemented by vboot as well as its requirement of a more complex partition scheme designed for chromeos to make use of the measured boot functionality implemented within vboot library to measure the boot process. TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook(). Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-03-30mb/google/kohaku: Add enable_delay_ms for wacom penEvan Green
Add an enable reset delay to avoid messages like this in the kernel: i2c_hid i2c-WCOM50C1:00: failed to change power setting. This gets rid of all the warnings except one on reboot/shutdown. That last case likely isn't fixed because the sleep command is being sent directly from i2c_hid_shutdown(), so no ACPI routines get to run and provide the delay. Since the machine is going down for shutdown/reboot anyway, fixing that last case is a lower priority. BUG=b:145094539 TEST=Run on kohaku, switch to guest mode and log out, no errors Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I8fadf497dd09e5b95b1d74443fb0543d3555dbb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-30mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-seriesAngel Pons
It is not a single mainboard anymore, it's actually three variants. Change-Id: I66f1239abadd8bf93269d6d4617329dc4b925e8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-30mb/gigabyte/ga-h61m-*: Use overridetreesAngel Pons
Make use of overridetrees, as these mainboards are very similar. Tested on GA-H61MA-D3V, still works fine. Change-Id: I1b587a091da631cb172eb76722958da6c7518893 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39668 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30mb/lenovo/t530: Switch to overridetreePeter Lemenkov
Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30asus/p2b-f: Transform into variantKeith Hui
TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I56983cabfad574b970aba098a178e691c6b354d1 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30asus/p2b: Transform into variant-enabled structureKeith Hui
Get ready to squash all the ASUS i440BX boards together. Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30mb/gigabyte/ga-h61m-s2pv: Correct PCIe port setupAngel Pons
Coalescing is not needed, as root port #1 is enabled. Also, update the comments to look more like the other two variants. Note that the Intel H61 PCH only has six root ports, so devices 1c.6 and 1c.7 do not exist. Change-Id: I3f4bf99ceec6c77f6e1eabea9b712245afee7d34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39742 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30mb/google/deltaur: Provide initial devicetreeTim Wawrzynczak
This initial devicetree attempts to correctly configure the status of each PCI device. Not all required drivers are instantiated, nor are all of the SoC options fully selected yet. PCIe root ports are enabled and clocks are assigned. USB ports are assigned. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30mb/google/deltaur: Add initial GPIO configurationTim Wawrzynczak
This configuration sets up all of the GPIO pads for the first rev of the board. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30mb/google/deltaur: add deltaur mainboard initial supportBora Guvendik
Created a new Google baseboard using Tiger Lake named deltaur, taking volteer as a starting point. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30tgl boards: Configure retimer Aux orientationBrandon Breitenstein
In order to create a working baseline all ports are being set to have retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimer. This setting is in the process of being documented in the TGL EDS and we can update once it is fully understood what this setting is changing on the SOC side. BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on Volteer, Connecting Type-c display should work regardless of Type-c cable orientation. Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30volteer: Create halvor variantFrank Wu
Create the halvor variant of the volteer reference board by copying the template files to a new directory named for the variant. BUG=b:151399850 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_HALVOR Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: If4d3417ba55d56af441c99d949a196328d7a1951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-30mb/tglrvp: Add GPE configurationShaunak Saha
Update the GPE configuration for dw0, dw1 and dw2. BUG=None TEST=build and boot tglrvp Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30mb/google/hatch/var/kindred: set wifi sar for kledDavid Wu
Enable wifi sar feature and set wifi sar name for kled sku. BUG=b:152277272 TEST=emerge-hatch coreboot chromeos-bootimage and verify wifi SAR load by sku-id Change-Id: I9ee242773fd05cc2bcd7bde07da8176022827677 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-03-29mb/google/glados: disable serial console by defaultMatt DeVillier
Glados boards do not have an exposed serial port outside of the servo interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot google/chell with board defaults Change-Id: Ifad6f805e66438e2c436d9fa235d9be2ecf69179 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-29drivers/intel/gma/acpi: Provide default definition for displaysNico Huber
Use it wherever the standard numbers were copied to. Bit 31 is set at runtime unconditionally, so we don't need it here. Change-Id: I0d853c3b8250a2c7b2d1a91985a555e4b17ad76c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39731 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29nb/intel/haswell: Implement proper backlight PWM configNico Huber
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code. We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT. Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29mb/google/cyan: Clean up KconfigMatt DeVillier
Cyan has no VGA BIOS available (at least not publicly), so remove related options. Disable SoC serial output by default, since no production devices have this exposed, but leave it as a user option so it can be selected as needed (eg, for use with a Google debug servo). Change-Id: Ic079a39ca5ad0ac653b52248244b94d4bfbd08a4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39872 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29mb/google/glados: remove Chrome-EC defaultsMatt DeVillier
Chrome-EC/PD images for all glados variants need to be built from the board-specific branch, not master. Including the default board names serves no purpose and requires users to deselect the "use built-in EC firmware" in order for the board to build. Test: build google/chell with defaults Change-Id: Ic10f11337b85035068cdc4fe8147413e6b7f57ac Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29mb/51nb/x210: Fix up USB ports in devicetreeMatt DeVillier
Add missing port definition for the mSATA/WWAN mPCIe port, set OC pin for internal ports to OC_SKIP, fix port descrption for mPCIe/WLAN port, remove USB3 definition for right type-A port as it is USB2 only. Test: insert WiFi module into WWAN port, observe BT portion detected and functional. Change-Id: Ie39b99eeb0f605ff07d57c32189fb1f4183713e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29hatch: Create sushi variantPaul Fagerburg
Create the sushi variant of the hatch reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 3.0.0). BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SUSHI Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-26mb/intel/cedarisland_crb: Add Cedar Island CRBAndrey Petrov
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26mb/ocp/tiogapass: Properly configure early serial outputAndrey Petrov
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible. This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible. TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock. Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-03-26mb/intel/jasperlake_rvp: add display related UPD configsRonak Kanabar
Change-Id: Iad0b394dea017223a5b92fff0cb4c2ed1d5a7bd7 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39402 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26mb/intel/jasperlake_rvp: Correct Kconfig optionsMaulik V Vaghela
1.Select CHROMEOS_EC related Kconfig for variant board with external EC support. 2.Select proper CHROMEOS Kconfigs which are required for all variants. 3.Disable Intel EC region in case of external EC. BUG=None BRANCH=None TEST=Compilation is successful for both Jasper Lake RVP variants. Change-Id: I290b3748777e18476651101de71df9080dd3105c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39584 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26mb/google/dedede: Query the EC for board versionDtrain Hsu
The board version is part of EC's EEPROM, select Kconfig item to enable requesting the EC for board version. BUG=b:152374066 TEST=Verified the mainboard version is from EC's EEPROM. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Idd8aceed83439cb500e2b03153e9f8ba93979ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-26mb/google/hatch/variants/nightfury: Replace unneeded white spaces by tabsElyes HAOUAS
Change-Id: Icda241cfac7b428176515d7996a48cb01b1dc976 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39815 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26mb/google/volteer: Use tabs for indentsElyes HAOUAS
Change-Id: I7304b06d7bf34fb7126acfdef811481dc5cba598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-26mb/facebook/monolith: Update GT-Sliced icc_maxWim Vervoorn
Update the icc_max for the GT-Sliced VR domain according to the hardware design. BUG=N/A TEST=build Change-Id: Ib9f7d77d144a282214e6bda8a4e836873c395487 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39804 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26drivers/net/r8168: Fix ethernet_mac[0-9] format for vpdEdward O'Callaghan
The format for VPD has changed s.t. the first NIC should always have a zero concat to the end. Adjust all the respective boards to shift back by one and adjust drivers/net friends to remove the 'special casing' of idx == 0. Background: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn V.2: Fixup a code comment typo while we are here. V.3: Vary special casing semantics for idx==0 => default mac addr is set. V.4: Rework to still support the legacy path. BUG=b:152157720 BRANCH=none TEST=none Change-Id: Idf83cc621a9333186dabb668b22c4b78e211930a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-26soc/intel/xeon_sp: Refactor code to allow for additional CPUs typesAndrey Petrov
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25create stdio.h and stdarg.h for {,v}snprintfJoel Kitching
Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create stdio.h and stdarg.h header files. Relocate snprintf into stdio.h and vsnprintf into stdarg.h from string.h. Chain include these header files from string.h, since coreboot doesn't care so much about the legacy POSIX location of these functions. Also move va_* definitions from vtxprintf.h into stdarg.h where they belong (in POSIX). Just use our own definitions regardless of GCC or LLVM. Add string.h header to a few C files which should have had it in the first place. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-25superio/nuvoton/nct5104d: add chip config option to reset GPIOsMichał Żygowski
Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-25mb/facebook/monolith: Configure COMB to 0x3e8Wim Vervoorn
The 2nd COM port's base address defaults to 0x2f8. Current software for this system expects the port at 0x3e8. Configure COMB to use 0x3e8 instead of 0x2f8. BUG=N/A TEST=tested on facebook monolith Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25mb/intel/jasperlake_rvp: Update FMAP for jslrvpMeera Ravindranath
Remove unused SMM_STORE space and use it for RW_LEGACY area BUG=None TEST=None Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-03-25mb/google/dedede: Update EC_MKBP_INT_L configurationKarthikeyan Ramasubramanian
The concerned GPIO is configured as an open drain at the Embedded Controller side without an external pull-up. This causes leakage in the PP3300_A rail. So configure the GPIO to have a weak internal pull-up at the SoC side. BUG=b:151680590 TEST=Build the mainboard. Ensure that there are no leakages in the PP3300_A rail. Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-25mb/intel/jasperlake_rvp: Add config check for lid switchMaulik V Vaghela
We should only define function to get lid switch and recovery mode switches when CHROMEEC_SWITCHES is not available. Correct this to avoid compilation issues BUG=None BRANCH=None TEST=jslrvp code compilation is fine Change-Id: I2445d40da1540c9d8c8c5fc845a4f38a5abf983e Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39585 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVPRonak Kanabar
Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 09:46:45 +0000