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2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Make Asus A8V-E SE better ACPI citizen.Rudolf Marek
Use the SSDT autogen infrastructure to support the automatic reserved resources, automatic P-state generation and automatic _CRS PCI0 method. Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-12avalue/eax-785e: Get SATA Mode from Kconfig optionKerry Sheh
Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/233 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12persimmon: complete the sb800 devicetreeKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. So the missing sb800 USB3 devicees was add to the mainboard devicetree. Because of no physical usb connector connected to USB3, the USB3 device setting was off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/232 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11mainboard: complete the sb800 devicetree even device is offKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/230 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11persimmon: sb800 sata mode configure updateKerry Sheh
persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/227 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
The hp/dl145_g1 motherboard did not work since commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process stopped very early (no console output whatsoever). The same symptom was reported on other AMDK8 based boards with amd8111 southbridge chips. This commit seems to fix the bug. It adds a bootblock.c under src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the problem was that enum_ht_chains needs to be called before the southbridge bootblock.c function, not after. Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/235 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-21Use ACPI text fields consistently with all other boardsStefan Reinauer
LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-17Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.Marc Jones
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/219 Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com> Tested-by: build bot (Jenkins)
2011-09-17Enable SATA AHCI for faster boot with SeaBIOS.Marc Jones
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/220 Tested-by: build bot (Jenkins) Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
2011-09-16Persimmon updates for AMD F14 rev C0efdesign98
These are the changes for the AMD Persimmon mainboard required to support the update of the AMD Family 14 cpu to rev C0. There are many warning fixes; the agesa- wrapper.c file has been changed to fix the amdinitlate and amdlaterunaptask routines, and more. Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/137 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15AMD Inagua platform updatesefdesign98
These changes update the Inagua platform. The changes include modifying the Kconfig to suggest video bios and ahci rom implementations, changing the dimm spd code to use the correct bus addresses, cleaning up the makefile a bit, and fixing a duplicate definition warning associated with the BIOS_SIZE value. Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/136 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15AMD Torpedo platform updatesefdesign98
This update fixes warnings and supports as necessary the Agesa infrastructure changes required to support the AMD Family 14 cpu update to rev C0. Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/138 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14Update to Asrock E350m1 for AMD F14 C0efdesign98
This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/139 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14mainboard: add avalue/eax-785 ITX mainboardKerry She
It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i. Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie slot, Lan, audio, PS2 keyboard/mouse and USB are verified. Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/208 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-04Disable dev3 on ma78gm-us2hWang Qing Pei
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/187 Tested-by: build bot (Jenkins)
2011-08-26X60/T60: remove obsolete dmi.hSven Schnelle
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/174 Tested-by: build bot (Jenkins)
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-08-25Minor ma785gmt clean-upAlec Ari
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25Fix up various dsdt.asl filesAlec Ari
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-24Remove dead codeAlec Ari
Remove dead code, copy and pasted from tilapia's mainboard.c file into various asus mainboard.c files Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-18X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/UndockingSven Schnelle
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/161 Tested-by: build bot (Jenkins)
2011-08-09Do not compile nuvoton superio for all boardAlexandru Gagniuc
The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/129 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-06ms7135: add ACPI supportJonathan A. Kollasch
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-04Add voltage control of southbridge and RAM on ms7135Jonathan A. Kollasch
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-16Workaround the errata #181.Rudolf Marek
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. The memory controller is enabled later, nor the workaround makes any harm to non-affected CPUs. This update unbreaks compilation by declaring the tmp variable. Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/69 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-14Move AMD SB800 early clock setup.Scott Duplichan
Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/96 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-13Enable SMI on M2V-MX SERudolf Marek
Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/83 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-11T60: enable GPIO before using GPIO I/O port rangeSven Schnelle
Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/93 Tested-by: build bot (Jenkins)
2011-07-11T60: dont use X60 USB init flagSven Schnelle
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/92 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/91 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-07T60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/89 Tested-by: build bot (Jenkins)
2011-06-29Added support for Aaeon PFM-540I RevB PC104 SBCMark Norman
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU. More infomation about the board available at www.aaeon.com. Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/30 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29amd southbirdge sb800 wrapper, pci bridge fixKerry She
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Add the AMD Torpedo mainboardefdesign98
The Torpedo mainboard is the reference platform for the AMD Family 12 cpus and the AMD Hudson-2 (SB900) southbridge. Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/54 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28X60: remove pci config register save/restoreSven Schnelle
SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/65 Tested-by: build bot (Jenkins)
2011-06-23T60: undock on external power lossSven Schnelle
If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/62 Tested-by: build bot (Jenkins)
2011-06-23T60: enable userspace EC eventsSven Schnelle
EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/61 Tested-by: build bot (Jenkins)
2011-06-23T60: add additional EC eventsSven Schnelle
We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/60 Tested-by: build bot (Jenkins)
2011-06-23Add ThinkPad modelsSven Schnelle
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/59 Tested-by: build bot (Jenkins)
2011-06-23T60: add missing License HeaderSven Schnelle
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/58 Tested-by: build bot (Jenkins)
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