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2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27southbridge/amd/pi: Rename Avalon to HudsonDave Frodin
To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27vboot2: read dev and recovery switchDaisuke Nojiri
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa Original-Reviewed-on: https://chromium-review.googlesource.com/206064 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1 Reviewed-on: http://review.coreboot.org/8162 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri
This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 Reviewed-on: http://review.coreboot.org/8160 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26rush: Add support for rush boardFurquan Shaikh
Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Reviewed-on: http://review.coreboot.org/8041 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-19samus: Update indices of ramstage and refcode blobsRandall Spangler
This must be committed at the same time as the corresponding depthcharge change which updates the fmap. BUG=chrome-os-partner:30079 BRANCH=none TEST=Build samus firmware. dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and PD_MAIN_B sections. Boot samus. 'crossystem mainfw_act' -> A As root, 'crossystem fwb_tries=1' Reboot samus. 'crossystem mainfw_act' -> B CQ-DEPEND=CL:208984,CL:*169850,CL:208989 Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208899 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837 Reviewed-on: http://review.coreboot.org/8219 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Delay bringing SSD out of resetDuncan Laurie
In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Disable self refresh and MRC cache on broadwellDuncan Laurie
Add workarounds for power and/or lpddr3 issues on Broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208154 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3 Reviewed-on: http://review.coreboot.org/8214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-19samus: Enable keyboard backlightDuncan Laurie
- Turn on keyboard backlight early in boot (not resume) path as a sign of life for the system - Add ACPI device for keyboard backlight so the kernel can find and make use of it BUG=chrome-os-partner:30586 BRANCH=None TEST=build and boot on samus Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208152 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4 Reviewed-on: http://review.coreboot.org/8213 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-19samus: add acpi resource for supporting RT5677 codecKane Chen
Add codec acpi resource for supporting RT5667 codec. BUG=chrome-os-partner:29649 TEST=emerge-coreboot successfully checked codec device is probed Original-Change-Id: I739c0dbfdbfa221b06f99c3d934825b640096c6b Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207707 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit f9698c45a47efe7fd2a1f5432640f3db5e4bd3f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib14b27421613d747e02037ecd2311d9966a5d813 Reviewed-on: http://review.coreboot.org/8212 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-17asrock/e350m1: Fix PCIe slot for x4 cardsKyösti Mälkki
Configuration for GNB GPP was incorrect, only PCIe x1 cards worked. Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8229 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-16rambi: configure USBPHY_COMPBG by the setting in devicetree.cbKane Chen
USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly CQ-DEPEND=CL:208557 Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208731 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75 Reviewed-on: http://review.coreboot.org/8217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-15mainboard/tyan/s2882/irq_tables.c: Remove dead code under #if 0Edward O'Callaghan
Silence unused variable warning. Change-Id: I2671e0843a60e5bd857b233a45ea68715461f187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8202 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-13mainboard/lenovo/x220/gpio.c: Remove unused structEdward O'Callaghan
Change-Id: I25bdee38cedbe38cd447483d3e8b3bdc3f646a62 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8201 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-12mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIOEdward O'Callaghan
These boards don't have Super I/O's, rather they use Embedded Controllers instead. No need to confuse with Super I/O related stuff showing up in menuconfig. Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7986 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-01-11mainboard/lenovo/x201/romstage.c: Remove unused functionEdward O'Callaghan
Function was orginally used for reverse engineering. Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8158 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2015-01-10ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10Fix mainboard names for daisy and peach_pitDavid Hendricks
This just fixes name members of mainboard_ops for daisy and peach_pit, which were never officially supported but used for development and proof-of-concept. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96 Reviewed-on: http://review.coreboot.org/8184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-10macbook21: Add CST entriesAxel Holewa
Due to the CST entries the machine uses less power running GNU/Linux-libre. This can be seen by monitoring CPU temperature and time left the machine can run on battery. CPU temperature measurements have been done with lm_sensors, battery querying with acpi. Tests have been done before applying this patch and after. In both cases the battery was fully loaded and the machine powered up on battery, without AC. In both tests the machine was idleing for more than 1 hour. Without this patch battery was predicted to last 01:52:30 hours, CPU temperature first measurement showed 38 degrees. After 15 min idle, temperature has reached its maximum value in this test of 61 and 62 degrees (Core 0 and 1). Fan speed begins to increase shortly after 15 min. From its minimal value 1800 rpm it reaches 3100 rpm after 40 min. CPU temperature did not increase any further. After 60 min idle, the battery was predicted to still last 57 min. With this patch battery was predicted to last 02:22:40 hours. That is plus 30 min. CPU temperature begins at 35 degrees. After 15 min temperature has reached 45 degrees; after 30 min it has reached the maximal temperature during this test of about 50 degrees. That is 10 degrees improvement. The fan stayed at minimal speed. After 60 min idle, the battery was predicted to still last 01:22:48 hours; a 25 minute improvement. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/7923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09AMD binaryPI 00730F01: Switch to per-device ACPIKyösti Mälkki
Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09samus: Updates from P2 buildDuncan Laurie
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d Reviewed-on: http://review.coreboot.org/8135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Enable EC ALS deviceDuncan Laurie
Enable the ACPI Device for the EC ALS. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d Reviewed-on: http://review.coreboot.org/8133 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09samus: Updates for P2 boardDuncan Laurie
- RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66 - LTE_POWER_ON connection removed BUG=chrome-os-partner:29502 BRANCH=None TEST=none yet, preparing for new board Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203186 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314 Reviewed-on: http://review.coreboot.org/8131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09storm: Increase DRAM size to 1024MBDavid Hendricks
BUG=chrome-os-partner:29871 BRANCH=storm TEST=builds and boots (sort of) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366 Original-Reviewed-on: https://chromium-review.googlesource.com/206011 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb Reviewed-on: http://review.coreboot.org/8148 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: USB fixes for proto0Vadim Bendebury
The actual storm device has a single USB interface, which needs to be explicitly turned on using GPIO51. BUG=chrome-os-partner:29871 TEST=verified that depthcharge finds and boots a kernel from USB stick Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205329 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7 Reviewed-on: http://review.coreboot.org/8147 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09misc: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. Instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the generic code pieces to use printk() on all non-ROMCC boards. Our two remaining ROMCC boards are fixed up in this commit: bifferos/bifferboard and dmp/vortex86ex. Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8115 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09src/mainboard: Doxygen fixesMartin Roth
- Remove @param command for #define - this isn't valid. - Rename duplicate @section names - All of the renamed @sections have other @section names in the same file. - Remove blank @brief and @param commands - Doxygen seems to REALLY dislike this... - Add a missing @param name. Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8175 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09mainboard/packardbell/ms2290/romstage.c: Comment unused funcEdward O'Callaghan
Take unused reverse eng function out of build by wrapping in #if 0. Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8167 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09asrock/e350m1, lenovo/x2x0 Kconfig: fix indentationNicolas Reinecke
Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8176 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09macbook21 lenovo/xx: Fix inw() in SMI handlersKyösti Mälkki
Missing base may have enabled SMI for all GPI inputs. Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8169 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06mainboard: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the mainboard code to use printk() on all non-ROMCC boards. Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8111 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06Drop VIA VT8235 southbridgeStefan Reinauer
It's unused. Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7883 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06AMD platforms: fix callout_entry doxygen errorsMartin Roth
Somewhere along the line, the sb_cfg parameter name was changed to config, but this wasn't carried into the documentation or the function prototypes everywhere. Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8098 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06AMD Mainboards - rd890_cfg.h: fix Doxygen errors.Martin Roth
Doxygen gives an error when processing #defines inside doxygen comments. Normal comments are ignored. The choice for this fix was to make this a standard comment starting with '/*' instead of '/**', or to make the comment not a #define. Change-Id: I97fbbcea6f045d80ec7c0ab5e196d57e5da16d86 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8099 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06AMD Mainboards - rd890_cfg.c: Fix doxygen warningsMartin Roth
Remove variable types from the param declaration. Change-Id: Ia6a3d36fcf01d7a52bb1a31cfdb47d88bf612d79 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8097 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06doxygen fixes: fix parameter names to match the functionsMartin Roth
The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06Remove AMD's "Release Content" doxygen from coreboot filesMartin Roth
These comments are left over and are not relevent in the coreboot code, but created a new section titled "Release Content" in the doxygen documentation produced by the coreboot code. In an effort to clean up the output, I'm removing these doxygen comments. Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8069 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06mainboard/*/romstage.c: Fix 'lib/delay.c' inclusionEdward O'Callaghan
Use 'delay.h' header rather than directly including 'delay.c' source. N.B. Some amdfam10 and K8 boards are not included in this changeset since unrelated issues are woven in there. Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8086 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06superio/smsc/lpc47n207: Hook into build systemEdward O'Callaghan
Provide proper Makefile and Kconfig components so that this superio is built as object code. Select superio component in mainboard Kconfig's to bring in the link-time symbols and thereby removing the need for .c inclusion. N.B. The LPC47N207 Super I/O does not physically exist on these boards. The Super I/O is found on external LPC debug card hardware and so should really be made selectable. However, this is beyond the scope of this specific fix, that rids us of .c inclusions in romstage.c Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8084 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-05hp/abm: Add new mainboardDave Frodin
The hp/abm board is used in network/server applications. Notes: - The hp/abm board is headless and therefore does not define CONFIG_GFXUMA, and does not require a video bios. - The micro USB connector on the board edge is connected to COM4 (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3. - If you are using SeaBIOS it would also need to be configured to use the UART at I/O=2E8h. - This board has been tested with headless installed versions of Ubuntu 12.10 and Fedora 19. Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6116 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-05Copy asrock/ibm-a180 to hp/abmKyösti Mälkki
Change-Id: I8dcb3912976d7381421dc41ee30e7c7652e6c28a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6115 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-04AMD Mainboards - romstage.c: Fix doxygen errorsMartin Roth
- Remove types from the param declarations. - list needed to be uppercase. Change-Id: I8b9ed78908e5d3e1d99e7ba2ea9013be109b8e27 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8072 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-04AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errorsMartin Roth
Remove PeiServices param for OemInitEarly - it doesn't exist in the function. Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8073 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-04AMD Mainboards - platform_cfg.h: Fixes for doxygenMartin Roth
- Move @def BIOS_SIZE description to the next line - SB_GEN2 changed to SB_GPP_GEN2 - Move the SIO_HWM_BASE_ADDRESS description to the next line Change-Id: Ia3496b0108484f557627304553461932a100dfa5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8071 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-04superio/smsc/lpc47b272: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: Id3d5f2a120c0a933c031102f206829305da20f0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8081 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 05:24:30 +0000