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The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.
Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop GENERIC_SPD_BIN from boards selecting it, despite having no
soldered memory.
Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert gpio.h to a compacter, cleaner format by keeping gpios in a
single line, where possible.
This was done with the following fancy vim regex replacement commands.
(Neither sed, nor awk multiline matching syntax are friends with me...)
Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before
pasting each command, press enter and see how the format changes.
g#^\t//#d
%s/^\t\t/\t/
g/PAD_.*$\n\n[^/]/s/\n//
g#// NC#d
%s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g
%s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */
%s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */#
Finally some indents and multiline comments need to be fixed manually.
Test: images built with TIMELESS do not differ.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which
is better understandable.
Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie106bbc8222dce60c837042a313d069289c79322
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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"post_code()" needs <console/console.h>.
Change-Id: Ice92d5e259b369da949006bf471a0cb249291897
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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It changes the binary for apple/macbook21 because of optimization of "Store" instruction.
Generated build/dsdt.dsl files are same.
Change-Id: I16b5180f8a8c44e6bc3ef353a99ef92a381b3295
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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After adjustment on madoo
Touch Pad CLK: 381.9 KHz
Touch Screen CLK: 389.4 KHz
Audio CLK: 380.9 KHz
BUG=b:168565823
BRANCH=master
TEST=USE=build madoo and measure by scope with madoo.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Convert the EC and touchpad interrupt pads from raw to macros. This
was done with intelp2m.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CSE Lite SKU is CSE FW designed for Chrome and this enables CSE Lite SKU
support for tglrvp.
BUG=None
TEST=Build and boot tglrvp with CSE Lite and Consumer SKU
Change-Id: Ia5f3e8125b5e7760a62f7fb46aeeae85c32e2037
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41132
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I3fdc521d30155c4275c336afe03244311f584e71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id51da519582856b1856479b641599e14f79fd1ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I051dc318c5f881bc58b1a4460faad6af22049b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: If56031a7b39d1c1b3ebf6d19376f19ec8c7cef1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I5274bc7206ba333d06f5defc35fdede540a7148f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I229d3995983a05cdd7fef1609a65f31b9f8f2969
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I3d0ca401cf5268962bcd9074f94c37724cc0a836
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I1aae6c0291ad329c8cc125cd18ba22dfd63d979b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ib56b56c05df154522172bff2e6746280286a481f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ief8df9ef0d6ecb675680aa5120738f5099034139
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45245
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If631055dffa79e7562d6238f6e0b88ad1c7d38b4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Id9837eda69d725539a82b3c98f63a57240051c5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I6dc9f153270fe501d53ab44c902401893aacf1b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ica6a885721b3a88814973d1cf086d2d4bc3d922d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I035b66e749e9a3e1bde13c8ed7ceafeb1edbbfa4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I82c2527039a9bd278e57cfbd88a009ee5ba03e1d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I76d5292871c1578f9d27d46b7a2c485a14c3017b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I2ceeae8dd25663203549a87b4e9524a631fa92f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Icad51da75d99dd541f8f2621a16eae13a596d264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Lets have the Kconfig depend more directly on CSE_LITE_SKU
than indirectly on the PUFF baseboard.
BUG=none
BRANCH=puff
TEST=builds
Change-Id: I8784b506629ceedc2770dc86d8caabbef5eb8a1d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45523
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.
BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add wifi sar for madoo.
Using tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165105210
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ic6128b966c952cdc02a6359c14fa41f22265039a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Fix this bit field to convert to target macros PAD_NC() macros.
This is part of the patch set
"mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values
CB:43567 - 2/4 Exclude fields for PAD_CFG
CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC()
CB:43410 - 4/4 Convert field macros to PAD_CFG
Change-Id: I73a3d78457c1e50dc9625a47394e340181516696
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43568
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch excludes bit fields that must be ignored (1,2) in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -fld cb -ign -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
- ignore RO bit fields;
- ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values
CB:43567 - 2/4 Exclude fields for PAD_CFG
CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC()
CB:43410 - 4/4 Convert field macros to PAD_CFG
Change-Id: Id0196b20783126c36f8552534b7ec3bd9049a24f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43567
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch excludes bit fields that must be ignored (1,2) in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -fld cb -ign -t 1 -file ../../src/mainboard/razer/
blade_stealth_kbl/gpio.h
- ignore RO bit fields;
- ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Change-Id: Ia36c5d0cd449a32d76351a87a33a55196ae78443
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43858
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the intelp2m utility [1,2] with -adv options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc...
./intelp2m -fld cb -t 1 -file ../../src/mainboard/razer/
blade_stealth_kbl/gpio.h
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
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Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc...
./intelp2m -fld cb -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set
"mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values
CB:43567 - 2/4 Exclude fields for PAD_CFG
CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC()
CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I19282c985cf35a9f99be449915aa9bab7e03472d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43566
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This sets the state of GSPI chip select to 1 (deasserted) as applied
by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS
mode manual in the SerialIoGSpiCsMode section which means we need to
explicitly configure CS to deasserted in the SerialIoGSpiCsState
section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We
were running into problems where the normal expected CS toggle
sequence to wake up CR50 did not work because CS was already asserted
when it was expected to be deasserted, leading to TPM timeouts.
BUG=b:168090038
TEST=booted on volteer, no more "TPM flow control failure" messages;
verified fingerprint enrollment still works.
Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor.
BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor:
> AUDIO=MAX98373_ALC5682I_I2S_UP4
ectool cbi set 6 0x00000400 4 2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add newly defined fields for presence of keyboard backlight and
number pad to the firmware configuration table.
We don't have a need to use these in coreboot (yet) but this
keeps the bit definitions in sync.
BUG=b:166707536
TEST=abuild -t google/volteer
Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The BIOS region size is 0xc00000, not 0xa00000. Correct this.
Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Enable SATA Link Power Management capability to be able to save power.
TEST: /sys/class/scsi_host/host*/link_power_management_policy exists.
Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop all options with zero-value, since they already default to 0.
Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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clamshell/tablet:
Slow_ppt_limit(W) 20
Fast_ppt_limit(W) 24
Slow_ppt_time_constant 5
Stapm_time_constant 200
Sustained_power_limit(W) 12
clamshell:
Temperature limit(C') 100
tablet:
Temperature limit(C') 70
BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
2. change mode and check "thermctl_limit" will change
Change-Id: I1eda1411766e446b673046236f7cc4015696521f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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