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Enable MMU in bootblock. Makes qemu look more similar to real hardware.
There's no real need to activate the MMU.
Tested on qemu-system-aarch64: 5 page entries are used out of 32.
Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace DSDT ACPI code and DSDT injection with a SSDT only solution.
The current implementation shows some issues on current Linux, which
might be due to external ACPI objects, which are then injected into
DSDT or the fact that those objects only use 3 characters.
Replace all the DSDT code with an SSDT generator.
Tested on HP Z220:
Boots into Linux with no ACPI errors. The SSDT can be disassembled.
Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Leverage the common sku id space helper encoders.
volteer uses the non-legacy SKU ID space.
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Leverage the common sku id space helper encoders.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPP_E0 as output for view angle management
Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9
Signed-off-by: Rajat Jain <rajatja@google.com>.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure below ESPI IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
Change-Id: I1e450d6e45242180de715746b9852634de2669c6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Enable Internal Gfx device.
2. Configure DDI0 for EDP.
3. Configure HPD and DDC suppport for DDI1/DDI2.
4. Configure HPD GPIOs.
TEST=Verify display on EDP panel in OS
Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The indirection of names is exceedingly confusing for ultimately the single
interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on
the PCH side.
This helps folks chase this indirection down through the code.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I663678a4c572fe80298f7388870d5cd403122b98
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Overwrite the default of 1 MiB with the actual bios region size
set in the stock IFD.
Allows to use payloads like TianoCore without manually touching
the CBFS_SIZE.
Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39073
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix PNP warning about missing devicetree entry for SUART1/2 by setting
register 0xF0 to a sane (default) value.
Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset
value of 0x0 is only defined for GPD pads. For any other GPIOs this maps
to 0x3.
On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and
GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical
to Chipset mapping not found".
Set the right value (0x3<<30) for the affected GPIOs.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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lippert/hurricane-lx doesn't exist anymore (see Change-Id: I87e3963).
Change-Id: I6d1c3a846c5bbb5fdc74178d0cf8a3cdaae1a010
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39076
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I55bf3004c728bb42ee51dfa917c58d97c56502cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38876
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Iad86755952204bb1a56ef341e626b0627a958467
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38870
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38875
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38877
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Iba1d020b9e565e3c6c89a97114084d72a00b2a55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38871
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: not tested on hardware.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: not tested on hardware.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic3fda4e598af8df9c9ddc97f7eb7fdcdaff6580b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38879
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I51d42f137fa539225bca5631bec38144ffd4f1d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38873
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Warning: not tested on hardware.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ifb50fd22f5ef4db204a3427e03430177cad211cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38866
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables the SATA config from devicetree for JSL RVP, since we
are not planning to use the SATA storage in chrome config.
Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9abc0837b72b13e7614ecffa5b21c3d4bf41d0f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add missing include <device/pci_def.h> for the boards that are being
switched away from ROMCC_BOOTBLOCK.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38903
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change creates gfx directory under drivers/ so that all drivers
handling gfx devices can be located in the same place. In follow-up
CLs, we will be adding another driver that handles gfx devices.
This change also updates the names used within the driver from
*generic_gfx* to *gfx_generic*. In addition to that, mainboard
drallion using this driver is updated to match the correct path and
Kconfig name.
TEST=Verified that drallion still builds.
Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:149813043
TEST=tested on sarien and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin.
This can save 1mW power comsumption.
BUG=b:149289256
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.
Mitigate this by clearing any pending EC events on S3 wakeup.
Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.
Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add initial support for waddledoo board.
BUG=None
TEST=Build the mainboard and variant board.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Turn on EMMC device and enable the HS400 mode. Configure the GPIOs
associated with EMMC.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Add USB port configuration in devicetree. Configure USB Over-Current (OC)
GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:147994020
TEST=tested on drallion and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Tested with BUILD_TIMELESS, no changes.
Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The serial number and UUID returned by DMI are retrieved from VPD.
The solution supports a 16 character "serial_number" and a 36 character
"UUID" string.
BUG=N/A
TEST=tested on monolith
Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Enable use of VPD for monolith. This will be used to store the UUID and
Serial number.
BUG=N/A
TEST=build
Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.
BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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