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2019-12-11mb/amd/padmelon: Use Prairie Falcon configurationRichard Spiegel
While Merlin Falcon binaries are not available, make it explicit that it's compiling for Prairie Falcon (it was being surreptitious about it). Board Padmelon accepts 3 different SOC, just changing some resistors (soldered or not): Brown Falcon, Prairie Falcon and Merlin Falcon. Code for Brown Falcon is not currently available. BUG=None TEST=Build with prairie falcon. Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-12-11soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and othersMarshall Dawson
Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbolMarshall Dawson
Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie FalconMarshall Dawson
The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11mb/**/hda_verb.c: use denary numerals for lengthsAngel Pons
Denary, also known as "decimal" or "base 10," is the standard number system used around the world. Therefore, make use of it. Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-11mb/portwell/m107/fadt.c Use get_apic_table_revisionFrans Hendriks
Fixed value of ACPI_FADT_REV_ACPI_2_0 is replaced by get_acpi_table_revision(). BUG=N/A TEST=build Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/goog/hatch/var/dratini: Tune i2c frequency to 400 KHzWisley Chen
Tuning i2c frequency for dratini: I2C0: 396 KHz I2C1: 398 KHz I2C3: unused I2C4: 394 KHz BUG=b:145891557 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37605 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/portwell/m107/acpi/superio.asl: Correct indentFrans Hendriks
Remove the additional tabs on all lines. BUG=N/A TEST=build Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/{facebook/portwell}: Define SDCARD_CD in dsdt.aslFrans Hendriks
SDCARD_CD is defined in onboard.h but required in ASL only, move this define to dsdt.asl. Removed the onboard.h file from the ASL files that don use it. BUG=N/A TEST=build Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/facebook/fbg1701/acpi/ec.asl: Remove headerFrans Hendriks
File contains header only. Remove header leaving an empty file. BUG=N/A TEST=build Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MBFrans Hendriks
Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc. BUG=N/A TEST=build Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/google/drallion/variants/drallion: Update thermal configuration for DPTFJohn Su
Follow thermal table for first tuning. BUG=b:144464314 TEST=Built and tested on drallion Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10mb/google/daisy: Move 'PMIC_BUS' to KconfigElyes HAOUAS
Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-10mb/{facebook/portwell}: Remove ITE8258_CMD_PORTFrans Hendriks
ITE8258_CMD_PORT is used in com_init.c only. Replace ITE8258_CMD_PORT by fixed value in the c file. ITE8258_DATA_PORT is removed as this isn't used. BUG=N/A TEST=build Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-10mb/google/kohaku: Update TCC offset settingSeunghwan Kim
This change sets TCC offset to 10 for kohaku. BUG=b:144532818 BRANCH=firmware-hatch-12672.B TEST=Checked thermal and performance efficiency internally (b:144532818) Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587 Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Grace Kao <grace.kao@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10mainboard/(i945,ich7): Remove commented RCBA32(0x341c) codeElyes HAOUAS
PCIe root port clock gate is already enabled at i945/early_init.c Also fix comments when only PCIe root port is enabled. Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09binaryPI boards: Bulk remove BINARYPI_LEGACY_WRAPPER remainsKyösti Mälkki
These boards currently have no build-testing, so they degrade fast. Apply some of the build-tested changes we know to be good from pcengines/apu2 to get them a bit closer to using POSTCAR_STAGE=y. Change-Id: Ibc9a15ed5e91c6dd857f2dd02e37d0979dd6ae90 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-09mb/lenovo/w530/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I0646b18e823c52109e0fb62c85726622156172b9 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37385 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/lenovo/s230u/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09mb/lenovo/t430s/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37300 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/lenovo/t430/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09mb/lenovo/x230/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09mb/lenovo/x220/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09mb/lenovo/l520/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09mb/lenovo/t420s/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37285 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/lenovo/t420/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-09mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variantBill XIE
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below) Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS. Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-09mb/google/octopus: Create Foob variantPeichao Wang
This commit creates a foob variant for Octopus. The initial settings override the baseboard was copied from variant phaser. BUG=b:144890301 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ibcdda4dd0846612f5e98ab454db7144c1caf0507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37456 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/intel/kblrvp: Remove hex values from VR settingsWim Vervoorn
Change the hex values in the VR configuration tables of the Intel Kaby Lake RVP boards to the same style that is used in the other mainboards. Also, correct some numbers in the comment tables that did not match the register values. The values in the tables haven't changed. BUG=N/A TEST=build Change-Id: I77af544d7d88143e19abedb12a13627779c705c6 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37550 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/google/poppy: set detachable system type for nocturne/sorakaMatt DeVillier
Set the SMBIOS system type to detachable for nocturne and soraka variants, to allow the OS to correctly process events. Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-09AGESA,binaryPI: Move PORT80 selection to C bootblockKyösti Mälkki
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-08mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CCElyes HAOUAS
Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-12-06mb/lenovo/w520/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-06mb/lenovo/t520/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37293 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-06mb/facebook/monolith: Add Facebook MonolithWim Vervoorn
The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.Philipp Hug
TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-12-05hatch: Fix FPMCU pwr/rst gpio handlingCraig Hesling
1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-05mb/intel/coffeelake_rvp: Switch to overridetree setupGaggery Tsai
This patch moves the common devicetree settings into baseboard and creates overridetree.cb for each variant. For PCIe root port settings, SATA, eMMC, I2Cs and GBe, they are in overridetree. TEST=build an image for each variant Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-05soc/intel/braswell: Use common sb code for SPI lockdown configurationArthur Heymans
This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-05mb/intel/icelake_rvp: Remove nested variant header referencesAamir Bohra
Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-12-05trogdor: Add mainboard USB supportT Michael Turney
Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-05mb/asrock/h110m: disable CLKREQ to use onboard LANMaxim Polyakov
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly. Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-05Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch"Kane Chen
This reverts commit 0bc35af93326ec3232ec73c9b1334241b85f0252. Reason for revert: This change breaks runtime s0ix. BRANCH=hatch BUG=b:141831197 TEST=Check slp_s0 residency increased when system is idle. Change-Id: Ida80f55b56de7129ed629eb29bd14f2ef300126f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04mb/google/octopus: Create Lick variantHash.Hung
Create new variant for Lick that is copied from phaser variant. Remove unnecessary code, due to not support touchscreen and stylus. Set to default_override_table. Remove variant.c. BUG=b:145181137 BRANCH=octopus TEST=./util/abuild/abuild -p none -t google/octopus -x -a Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174 Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04mb/google/drallion/variants/drallion: Adjust all I2C CLK to meet specJohn Su
After adjustment on Drallion Touch Pad CLK: 393 KHz Touch Screen CLK: 381 KHz H1 CLK: 391 KHz BUG=b:144245601 BRANCH=master TEST=emerge-drallion coreboot chromeos-bootimage measure by scope with drallion. Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04mb/google/kohaku: Adjust I2C clock frequencySeunghwan Kim
All serial I2C bus frequencies should not be over 400KHz in kohaku, but the measurement showed frequencies of I2C1 and I2C4 were over 400KHz. (b:144885961) This change adjusts I2C speed settings to limit that frequencies to 400KHz. The new setting values have been from other projects using same I2C components, and verified I2C1 and I2C4 frequencies < 400MHz internally. BUG=b:144885961 BRANCH=firmware-hatch-12672.B TEST=Verified I2C1 and I2C4 frequency not over 400KHz Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-04mb/google/hatch/var/akemi: tune DPTF for AkemiPeichao Wang
Tune DPTF to ensure compliance with Akemi thermal design requirements BUG=b:144195069 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-03hatch: Create stryke variantDtrain Hsu
(Auto-Generated by create_coreboot_variant.sh version 1.0.0). BUG=b:145101696 TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_STRYKE Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 21:11:22 +0000