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2020-06-06mb/google/dedede: Drop .spd.hex files from spd/Furquan Shaikh
Now that dedede is moved to using the auto-generated SPDs, we no longer need the .spd.hex files in spd/ folder. Hence, this change drops the files. Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Switch to using auto-generated SPDsFurquan Shaikh
This change switches dedede and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Drop selection of GENERIC_SPD_BINFurquan Shaikh
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it already provides its own rules for SPD inclusion. In follow up changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool to use similar suffixes and allowing different paths to be provided for SPD by mainboard. Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by wheelie and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledee and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Byte# Current New Explanation 4 0x14 0x15 This part has only 1 die. Hence, density per die is 8Gb. 6 0x90 0x04 1 die in package and 2 channels per die. Manufacturer name bytes are set to 0. Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/volteer: Drop spd/ folders from variants/Furquan Shaikh
Now that volteer is moved to using the auto-generated SPDs, we no longer need the spd/ folder under each variant. Hence, this change drops the spd/ folders and the SPD files within them. BUG=b:156126658 Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer: Switch to using auto-generated SPDsFurquan Shaikh
This change switches volteer and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. BUG=b:147321551,b:155423877 Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by volteer and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Part: K4UBE3D4AA-MGCL Byte# Current New Explanation 6 0xB5 0xB4 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. Part: H9HCNNNBKMMLXR-NEE Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: H9HCNNNFAMMLXR-NEE Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 6 0xF9 0xB8 This device has 4 logical dies instead of 8. Also, signal loading is not used by MRC. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS 22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value should be 0x12,0x29,0x15. 24 0x8C 0x96 taa is .468ns * CAS-40 which results in byte 24 being 0x96 as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x04C0. 123 0x00 0xE2 Fine offset for taa. Expected value is 0xE2 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G32D2NP-046 WT:A Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB5 0x94 This device has 2 logical dies. Also, MRC does not use signal loading. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 12 0x0A 0x02 As per datasheet, this is 1rank and 16-bit wide channel. So, value should be 0x02. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to 380ns in MTB units which is 0x0BE0. 31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to 190ns in MTB units which is 0x05F0. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by halvor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: H9HKNNNCRMBVAR-NEH Byte# Current New Explanation 4 0x16 0x15 As per datasheet, density is 8Gb per logical channel. So value should be 0x15. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels 2 dies. Hence, 0x94 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x0460. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G64D4SQ-046 WT:A Byte# Current New Explanation 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels, 2 dies. Hence, 0x94. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by malefor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/ripto: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by ripto and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede/board_info.c: Clean upElyes HAOUAS
Remove unused includes Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06arch/x86: Declare permanent_smi_handler()Kyösti Mälkki
Advertising SMI triggers in FADT is only valid if we exit with SMI installed. There has been some experiments to delay SMM installation to OS, yet there are new platforms that allow some configuration access only to be done inside SMM. Splitting static HAVE_SMI_HANDLER variable helps to manage cases where SMM might be both installed and cleared prior to entering payload. Change-Id: Iad92c4a180524e15199633693446a087787ad3a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06mb/emulation/qemu-q35: Control SMI related FADT entriesKyösti Mälkki
If running on older (like before 2.4.0) version of QEMU there is no SMI support, so never advertise SMI in FADT for the emulation. Behaviour if ACPI daemon tries to raise SMI under these conditions is unknown. Change-Id: I170058793798648c6713de1530d89ec2ac53e39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06mb/lenovo/t400,x200: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Ia61e50fb49719e9e18e81a27f355cdbd755a3f40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/roda/rk9: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/prodrive/hermes: Add new mainboard portChristian Walter
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-05google/trogdor: Remove RO_FSG regionJulius Werner
We decided to store the FSG on eMMC instead of SPI flash, so we don't need this region anymore. Getting rid of it allows us to put more space into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining amount to keep the FMAP alignment reasonable. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-06-04Revert "mb/google/zork: Increase RO section to 5MB"Raul E Rangel
This reverts commit fddd101904188193197be10c8eae04e76386299b. Reason for revert: With FSP compression and non serial FSP we now have enough space in RO. Original change's description: > mb/google/zork: Increase RO section to 5MB > > The current size is too small to fit all the depthcharge assets. > Increasing it to 5MB gives us 648k of free space. > > $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT > FMAP REGION: COREBOOT > Name Offset Type Size Comp > cbfs master header 0x0 cbfs header 32 none > fallback/romstage 0x80 stage 524316 none > fallback/ramstage 0x80100 stage 96592 none > config 0x97ac0 raw 843 none > revision 0x97e80 raw 680 none > spd.bin 0x98180 spd 8192 none > etc/sdcard0 0x9a1c0 raw 8 none > locales 0x9a200 raw 141 LZMA (166 decompressed) > (empty) 0x9a300 null 3224 none > fspm.bin 0x9afc0 fsp 720896 none > (empty) 0x14b000 null 3992 none > fsps.bin 0x14bfc0 fsp 327680 none > pci1002,15d8,c1.rom 0x19c000 optionrom 54272 none > pci1002,15d8,c4.rom 0x1a9480 optionrom 54272 none > fallback/dsdt.aml 0x1b6900 raw 12727 none > locale_hi.bin 0x1b9b00 raw 10441 LZMA (239928 decompressed) > ... > locale_ko.bin 0x254f80 raw 11282 LZMA (231168 decompressed) > fallback/payload 0x257c00 simple elf 95169 none > (empty) 0x26f000 null 245656 none > apu/amdfw 0x2aafc0 raw 1277440 none > (empty) 0x3e2e00 null 688472 none > bootblock 0x48af80 bootblock 64 none > > BUG=b:130028876 > BRANCH=none > TEST=Built image with depthcharge and booted. > > Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1 > Signed-off-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850 > Reviewed-by: Martin Roth <martinroth@google.com> BUG=b:130028876, b:150746858 BRANCH=none TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle localhost ~ # flashrom -p host -r /tmp/main.bin flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) Calibrating delay loop... OK. coreboot table found at 0xcbe54000. Reading flash... SUCCESS localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3 area: 22 area_offset: 0x00c00000 area_size: 0x00400000 (4194304) area_name: WP_RO localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. SUCCESS localhost ~ # flashrom -p host --wp-status flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. WP: status: 0x0094 WP: status.srp0: 1 WP: status.srp1: 0 WP: write protect is enabled. WP: write protect range: start=0x00c00000, len=0x00400000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-04mb/google/volteer: Create voxel variantDavid Wu
Create the voxel variant of the volteer reference board BUG=b:157879197 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOXEL Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8ba5412be211730db84675927c500238cb20ff3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-04mb/google/zork: create new variant for VilbozPeichao Wang
BUG=b:157499341 BRANCH=NONE TEST=FW_NAME="vilboz" emerge-zork coreboot Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41801 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03mb/google/zork: Add HID for max98357aRaul E Rangel
The default HID was removed by a1c82c5ebee. We need to explicitly specify it. BUG=b:154756391 TEST=No longer see ERROR: _HID required message in console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-03mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetreeArthur Heymans
These devices never show on the PCI domain. Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/gigabyte/ga-g41m-es2l: Add PEG to devicetreeArthur Heymans
Change-Id: Icebf0eea4e1fee6d15ba3f1a080cbc40b42fd733 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/aopen/dxplplusu: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Board does not support ACPI S4 or C-states or P-states. Change-Id: If83efb72e076d404468259e312a5afac625f04af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03Makefile: Drop HAVE_SMI_HANDLER test for smm-classKyösti Mälkki
Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubsKyösti Mälkki
Board does not have ChromeEC. Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC testsKyösti Mälkki
Boards have unconditional select EC_GOOGLE_CHROMEEC. Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/bap/ode_e21XX: Drop old commented KconfigsKyösti Mälkki
Change-Id: I56225c0a533e5f9e8294b7866a41c9a6c24a7f67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03mb/google/zork: Delete sb_fch.aslRaul E Rangel
This file is not used. BUG=b:154756391 TEST=Build trembyle and check that peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/hatch: Enable the CSE Lite SKU for Puff variantsV Sowmya
This patch enables enables the CSE Lite SKU for all the puff variant boards. BUG=b:143229683 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/hatch: Modify the puff fmd files to support CSE Lite SKUV Sowmya
This patch modified the puff fmd files to support CSE Lite SKU. * Reduce the SI_ALL size to 3MiB since ME binary size is less than 2.5MiB. * Increase the FW_MAIN_A/B size to accommodate the ME_RW update binary with CSE Lite SKU. BUG=b:154561163 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03mb/google/volteer/halvor: initialize gpio setting and update overridetree.cbFrank Wu
Based on schematic and gpio table of halvor, generate gpio setting and overridetree.cb for halvor. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the image-halvor.bin is generated successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/deltaur: Change H1 I2C speed to FASTEric Lai
H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM. Therefore change I2C speed back to FAST. BUG=b:154885320 TEST=Check H1 I2C speed is 375kHz by scope. And no error message in cbmem and kernel log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If58721039d90514a17f024e6b432f3a5226440e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-06-02mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllersJohn Zhao
This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting. BUG=:b:146624360 TEST=Built and booted on TGL RVP. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02mb/google/volteer/ripto: Add audio devices to the treeDuncan Laurie
The ripto board is still being used for testing so make sure it supports the same audio config as volteer. BUG=b:147462631 TEST=build ripto variant Change-Id: Iabeb73307418dc16b12fa60ad26923cd9f6e1f3a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-06-02mb/google/volteer: Add firmware configuration probing for audioDuncan Laurie
For all of the audio devices in devicetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others BUG=b:147462631 TEST=test different device present in ACPI based on fw_config value: > AUDIO=NONE ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682I_I2S ectool cbi set 6 0x00000200 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000300 4 2 Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41216 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Add firmware configuration tableDuncan Laurie
Add the current firmware configuration table for the volteer mainboard and define some actions based on probe results for audio: - When I2S options are selected disable the SoundWire GPIOs. - When SoundWire is enabled disable the I2S GPIOs. - When no audio is enabled disable all the GPIOs. BUG=b:147462631 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi. Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Reorganize audio codecsDuncan Laurie
- Move all audio devices from baseboard to the volteer variant. - Add max98373 devices and enable the driver - Disable everything in FSP and let coreboot configure GPIOs. BUG=b:147462631 TEST=this change makes all audio devices show up in ACPI, so this was tested by ensuring that all audio devices are present in ACPI. Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPMKyösti Mälkki
Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02mb/purism/librem*: drop EC chip deviceMatt DeVillier
CB:35086 exposed that the devicetree listed an EC chip for which there is no actual driver; the EC is entirely ACPI code (.asl) included by the board's ec.asl. Remove the unnecessary EC chip driver from both boards, as well as the unnecessary Kconfig selection for librem_bdw. Test: build/boot Librem 13v1, 13v4, verify battery info etc still correct. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02mb/lenovo/x230: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad X230 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291 Signed-off-by: Stefan Ott <stefan@ott.net> Tested-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40669 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vbe.h>'Elyes HAOUAS
Change-Id: I7c0be437e8cb49934913563c6d21056034a50095 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cbfs.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove duplicated includesElyes HAOUAS
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused 'include <arch/smp/mpspec.h>'Elyes HAOUAS
Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 05:40:03 +0000