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2014-04-12hp/pavilion_m6_1035dx: Declare GPIO control block in ACPIAlexandru Gagniuc
Only the WLAN control pin and the lid switch input are declared, as those are the only pins whose function is known and tested. Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5463 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12hp/pavilion_m6_1035dx: Add ACPI support for reading battery levelAlexandru Gagniuc
Hook in the EC ASL code. This provides just enough information for the OS to be able to read the battery information. EC notifications (_Qxx) do not yet work, and it is unclear if the issue is in the ACPI code, or if the EC is not set up properly. Thus, the OS must boot with the battery inserted in order to be able to read its status. The _L03 ACPI method is also removed, as the EC SCI uses this event. Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-12ec/compal/ene932/acpi: Let mainboard define the ACPI lid objectAlexandru Gagniuc
The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Also, document the ACPI interface for the EC. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5444 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-09supermicro/h8qgi/dsdt: Use PIC as default interrupt modelKonstantin Aladyshev
According ACPI specification: """ The \_PIC optional method is used to report to the BIOS the current interrupt model used by the OS. The argument passed into the method signifies the interrupt model OSPM has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the method is never called, the BIOS must assume PIC mode. Arguments: (1) Arg0 – An Integer containing a code for the current interrupt model: 0 –PIC mode 1 –APIC mode 2 –SAPIC mode """ In current configuration with default value of interrupt model PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option. Kernel never call _PIC method and PMOD stays equal 1, indicatind that APIC routing objects should be evaluated. This mix of PIC and APIC leads to boot fail. Change default value of interrupt model PMOD to 0, for correct "noapic" boot. Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/5473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09mainboard/lenovo: [2/2] implement initial T530 supportEdward O'Callaghan
Step 2: change the Lenovo X230 code to adapt it to the new board's hardware with the great guidance from Vladimir (phcoder) to find the correct GPIO's. The machine has: - Chipset: Intel QM77 - GPU's: Intel Integrated HD Graphics : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5391 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09mainboard/lenovo: [1/2] fork X230 to T530Edward O'Callaghan
Step 1: copy all files unmodified from Lenovo X230. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5390 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-04-09asus/f2a85-m: conditionally show POST codesIdwer Vollering
Change-Id: I61e55601676c0825815d6520a874ccade8942379 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09OxPCIe uart: Split PCI bridge controlKyösti Mälkki
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()Edward O'Callaghan
Follow same reasoning as: 12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio() Use coreboot variants for PCI and MSR access over AGESA's. Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5472 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tablesAlexandru Gagniuc
Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5462 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09supermicro/h8qgi/dsdt: Move _PIC method to root scopeKonstantin Aladyshev
_PIC method should be declared under root scope (\_PIC), otherwise Linux kernel doesn't use it. Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/5478 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()Alexandru Gagniuc
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access, use the coreboot variants, which are cleaner and more readable. Change-Id: I4f24820606900e16f0d159df019f4560f1592489 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-07hp/pavilion_m6_1035dx: Remove inexistent devices from devicetreeAlexandru Gagniuc
This removes ominous "PCI: xx:xx.x not found" messages from coreboot console. Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5461 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-06asus/f2a85-m: Sanitize #includesIdwer Vollering
Based on the same reasoning as this commit: 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5420 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-06superio/winbond/w83627thg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06jetway/nf81-t56n-lf: Sanitize #includesEdward O'Callaghan
Following the same reasoning as commit 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this board support. Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5414 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/winbond/w83627ehg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5448 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-03hp/pavilion_m6_1035dx: Sanitize #includesAlexandru Gagniuc
There were a number of things wrong with the includes. First, The includes did not use paths to AGESA files, thus relying on the compiler include paths to find the correct file. This made it unclear where the file included was located, and whether it was local, under vendorcode, or under a different directory. Instead, use full paths for each non-local include. Second, the local includes were mixed with the rest, making it unclear which file is local and which one is not. Keep the local includes at the top. This also prevents us from polluting the namespace of local headers, with library definitions, and allows us to catch if we missed an otherwise needed external header. Thirdly, alphabetize the order of includes where possible. Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5412 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-03lenovo/x60: Remove duplicate console_init()Kyösti Mälkki
For romstage, console_init() was called twice. The one in dock_connect() should have done only UART programming and not touch CBMEM console and/or USBDEBUG when those are enabled. Second case where dock_connect() is called is in SMI handler. If DEBUG_SMI is not enabled, console_init() does nothing in SMM. If DEBUG_SMI is enabled, console_init() is already called every time when enterining SMM. Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5433 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-02superio/fintek/f71859: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5417 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71863fg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I863c16634873224c17e43100271e9b91419724d0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5435 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71805f: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5434 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-01Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATEKyösti Mälkki
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the board properly implements EARLY_CBMEM_INIT. Flag vulnerable boards that only do cbmem_recovery() in romstage on S3 resume and implementation with Intel FSP that invalidates cache before we have a chance to copy the contents. Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-31superio/fintek/f81865f: Avoid .c includesEdward O'Callaghan
We should not be #include .c files, instead link early_serial into romstage and provide a prototype. Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5416 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-29cubieboard: Enable the SD controller and mux SD pinsAlexandru Gagniuc
This step needs to be done before calling any MMC functionality. Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-28mainboard/hp: Add initial support for Pavilion m6-1035dxAlexandru Gagniuc
This was a pathetically easy port, where all the components are already supported. This is basically a verbatim copy of amd/parmer. The EC is an ENE KB932, which is a part that does surprisingly little for an EC. This also means we need almost no code to get it working. I've "select"ed the EC in Kconfig, which is the only difference from parmer, although the keyboard worked fine without it. I haven't coupled in the ACPI code from the EC yet, so battery level is not readable from the OS. Hotkeys work except for brightness control, and the CapsLock LED blinks at regular intervals instead of following the CapsLock key. Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5409 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`Paul Menzel
It's not needed and causes build failures without CONFIG_CHROMEOS. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5398 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-26mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in KconfigEdward O'Callaghan
Switch on ACPI suspend/resume support which now works after many cycles. Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5406 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-24mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cbEdward O'Callaghan
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5401 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-17mainboard/lenovo/x230 Fix usage of GNU field designator extensionEdward O'Callaghan
In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5392 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-13mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.Edward O'Callaghan
The target board has a different base addr. for its hardware monitor (fans, temp, etc) from the Fintek Super I/O datasheet. Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5383 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.Edward O'Callaghan
Fan controls in 0x400-0x4ff are not programmed here. Thus fan control from amd/persimmon in the devicetree.cb does not apply to this board. Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5381 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11rambi: Enable USB boot with EHCI controllerDuncan Laurie
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-10AMD Olive Hill: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Olive Hill. Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4301 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10AMD Parmer: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Parmer. Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4302 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-09mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.Edward O'Callaghan
This board has a working PS/2 port for a keyboard. Thus, it makes for a good option to have on by default. Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5357 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.Edward O'Callaghan
The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5355 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-09intel/jarrell: Apply ROMCC workaroundKyösti Mälkki
Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08ROMCC: Trigger internal compiler failure and apply the workaroundKyösti Mälkki
These boards first failed when attempting to change print_err() from direct function call to console_tx_XX() to a code block in the form of do { if (y) console_tx_XX(x); } while(0) Removing the label dummy_romcc_workaround_label added here will trigger the following compiler error for the two boards: Internal compiler error: no edge to block->last->next Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5349 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08qemu-i440fx: add a prototype for main()Patrick Georgi
This probably belongs elsewhere, but I haven't found a nice place yet. Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04pl011 UART: Move under drivers/uartKyösti Mälkki
Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5162 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart: Drop HAVE_UART_MEMORY_MAPPEDKyösti Mälkki
This option is used to make uart8250mem option visible in menuconfig. Showing it for these ARMs is incorrect. Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04jetway/nf81-t56n-lf: Minor corrections to devicetree.cbEdward O'Callaghan
The miniPCIe ports hanging off 15.0 are infact x1, as are the two onboard NIC's on 6.0 and 15.0. Change-Id: I6247838f6b5823369543e338975a4c5c6fd00d7c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5328 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04jetway/nf81-t56n-lf: Fix PS/2 ACPI for KBC & Mouse.Edward O'Callaghan
Provide ACPI table node so that the PS/2 keyboard/mouse port works in GNU/Linux. Change-Id: If73b8d37a81bb9066cbcc650b518d25e243b84e7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5327 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04nehalem: Replace video init.Vladimir Serbinenko
Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03qemu: Support textmode gfx init.Vladimir Serbinenko
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5283 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03nehalem/raminit: Don't touch clock generator in raminit.Vladimir Serbinenko
Clock generator is mobo-specific. Don't touch it in raminit. Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5265 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-01lenovo/x60: Unify volume button handling with common code.Vladimir Serbinenko
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5099 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 11:45:20 +0000