summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2010-09-27RAMBASE = 0x4000 is no longer needed. Drop it.Stefan Reinauer
Now we only need to clean out the FAM10 stack mess and we're good to go with a uniform RAMBASE. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27Add a kconfig option to allow the user to select a specific physicalUwe Hermann
USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26i82801bx defines the hard reset function, so move the "select" statement toWarren Turkal
that component rather than the mainboard. The intel/d810e2cb is the only board using the i82801bx southbridge. Signed-off-by: Warren Turkal <wt@penguintechs.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26Remove hard reset config from some mainboard configsWarren Turkal
Most of the mainboards with i82801gx SBs seem to use the HAVE_HARD_RESET, which is already selected in the i82801gx SB config. Removing it from some of those boards should be a functional no-op. Signed-off-by: Warren Turkal <wt@penguintechs.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26Normalize the config option for the Intel Atom CPU.Warren Turkal
All Intel CPU models appear to be identified with the form INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form. A side effect is that the CPU doesn't need to be listed on the boards that support it since the socket identifies the CPUs it supports. Signed-off-by: Warren Turkal <wt@penguintechs.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Drop some useless "../../../" in #includes (trivial).Uwe Hermann
Build-tested using abuild. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).Uwe Hermann
Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix). Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do elsewhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Various USB Debug Port fixes (trivial).Uwe Hermann
- Drop unused DBGP_DEFAULT #defines on boards with chipsets where no USB Debug Port support is implemented anyway (at the moment, at least): - hp/dl145_g3 - hp/dl165_g6_fam10 - ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges with Debug Port hardcode the physical USB port used as Debug Port to 1. In other words, this port is not user-configurable (as seems to be the case on NVIDIA MCP55). For now we keep the 'port' parameter in order to not change the API, this might be fixed differently later. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Keep the mc146818rtc.h include close to the option table include whereMyles Watson
possible. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25- Fix race condition in option_table.h generation by moving the includeStefan Reinauer
statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Automatically fetch bus information for mptable fromPatrick Georgi
the device tree, instead of using hardcoded values. If this changes behaviour, this is either - a bug in mptable_write_buses(), or - a bug in the old mptable or device config, that is they were inconsistent. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Undo stupid mistake in r5832Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.Uwe Hermann
Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Fix hp/dl165_g6_fam10 build. Failed to take r5800 andPatrick Georgi
another recent change into account. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Add support for HP DL165-G6 with Fam10 CPU.Arne Georg Gleditsch
Original patch was Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Updates to accomodate changes in coreboot are Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-23Fix some wrong capitalizations, reformat comments, fix a typo.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-22 Here is a proposed way how to handle the SATA PHY settings on SB700. It Rudolf Marek
consits of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21Cut the crap.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-19Make ASUS P3B-F RAM init actually work by enabling SPD access.Uwe Hermann
On this board all reads from SPD return 0xff by default, there's a custom GPIO fiddling needed to enable access to the SPD SMBus offsets at 0x50-0x53. While coreboot actually sort of booted sometimes before r5193, that was just sheer luck as the RAM init was hardcoded in certain ways. Since the proper, more heavily SPD-based RAM init the brokenness of the ASUS P3B-F RAM init was becoming visible. This patch uses GPIOs to enable access to the SPD SMBus offsets, and resets the GPIOs again after RAM init (this is needed to allow for lm-sensors to work, for example). Tested successfully on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13IEI Kino added to IEI mainboard Kconfig. I missed this in r5812Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13IEI Kino mainboard support based on Mahogany Fam10.Marc Jones
svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13Add support for Asus M4A785-M.Juhana Helovuo
Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13Convert i945 boards to use reserved resources instead of directly addingMyles Watson
coreboot table entries in every mainboard. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,Jens Rottmann
CS5536, ITE IT8712F). Board support is based on the SpaceRunner-LX (with tiny bits from the RoadRunner-LX) even though the hardware really was the ancestor of our three other -LX boards and in fact among the earliest Geode-LX boards on the market. (Might even have been the first Geode-LX EPIC?) Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10Move memory type information out of some AMD sockets.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch
fixes a few alignment wrinkles and sets up and registers the MMCONF area for AMD Fam10h CPUs (where selected by mainboard configuration). It removes a bit of code that proved troublesome in MMCONF setups from mcp55_early_setup_car.c, as per earlier discussion. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMDJens Rottmann
Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07Remove unused ide0_enable and sata0_enable entries from SB7xx Rudolf Marek
and SB600. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07Set up an arbitrary amount of system memory on Geode LX, soAurelien Guillaume
coreboot_ram can be unpacked to 1MB. The value is quickly replaced with the real value later, thus causing no harm. Move RAMBASE to the default of 1MB for the affected boards Signed-off-by: Aurelien Guillaume <aurelien@iwi.me> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-06Instead of requiring users to modify qemu to allow writes toKevin O'Connor
0xc0000-0xfffff, have coreboot qemu support enable the memory range at startup. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-03Update RoadRunner and SpaceRunner config to get in sync with currentJens Rottmann
standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-02Fix compilation for mtarvon. CAR initialization does early_mtrr_init,Myles Watson
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-02Revert 5762. It silently broke a lot of boards because abuild was broken.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-01Fix race condition in option_table.h generation by moving the include statementStefan Reinauer
to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) Also, drop the AMD DBM690T work around for the issue. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31SMC_CONFIG is needed before the device tree is ready and some peopleJens Rottmann
would rather not have mainboard settings like sio_gp1x_config in the device tree anyway. So found a nice united home for both in Kconfig, where users can change them without having to mess around in the C code. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31Make ALIX.2D3 support 2D2 as well.Jens Rottmann
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30We call this cache as ram everywhere, so let's call it the same in KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Fix intel mtarvon compilation by switching it over to CAR.Stefan Reinauer
This should be unproblematic, as there are other boards with the same "socket" that work with CAR already. Tests are highly appreciated though! Acked-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Restructured all vendors' Kconfig files to no longer source the boards'Jens Rottmann
Kconfigs from within the choice/endchoice block. This makes it possible to define user visible board specific options. Moved all vendor names and PCI ids to the vendors' Kconfigs. Now all options in each file depend on the same symbol, so replaced all "depends on"s with a single "if". Sorted boards (sort -d), cleaned whitespace. This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is always "y" and never used. It it simply needed to have something to attach the boards' "select" statements to. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Support for Lanner EM-8510 BoardAndreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> --- src/mainboard/Kconfig | 8 ++ src/mainboard/lanner/Kconfig | 8 ++ src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++ src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++ src/mainboard/lanner/em8510/chip.h | 23 +++++++ src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++ src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++ src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++ src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++ src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++ 10 files changed, 418 insertions(+), 0 deletions(-) create mode 100644 src/mainboard/lanner/Kconfig create mode 100644 src/mainboard/lanner/em8510/Kconfig create mode 100644 src/mainboard/lanner/em8510/Makefile.inc create mode 100644 src/mainboard/lanner/em8510/chip.h create mode 100644 src/mainboard/lanner/em8510/cmos.layout create mode 100644 src/mainboard/lanner/em8510/devicetree.cb create mode 100644 src/mainboard/lanner/em8510/irq_tables.c create mode 100644 src/mainboard/lanner/em8510/mainboard.c create mode 100644 src/mainboard/lanner/em8510/romstage.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27drop three unneeded config variables:Jens Rottmann
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26Remove unused mainboard_config definitions. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /Jens Rottmann
chipset support it. But this involves a long list of 'depends', which you have to remember updating manually. Converted this into HAVE_... properties, which will be inherited automatically if someone copies a chipset to create a new one. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26kontron 986lcd-m: Fix compilation if there is no oprom execution at all...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-25Fix i945 based boardsStefan Reinauer
- prevent GCC from inlining do_ram_command - it will break RAM initialization. - fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not 200us - move PCIRST# as early as possible (before ich7_enable_lpc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-24* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.Aurelien Guillaume
* DRAM initialization done message is now printed in debug-mode only, rather than everytime. Signed-off-by: Aurelien Guillaume <aurelien@iwi.me> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20Remove a couple of warnings. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20Add support for the HP DL145 G1, based on the Tyan s2881.Oskar Enoksson
Signed-off-by: Oskar Enoksson <oskeno@foi.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-18The attached file add pa78vm5 dev3 detection function to avoid the building ↵Wang Qing Pei
error. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc ↵Rudolf Marek
needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 18:08:22 +0000