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2020-07-05mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_initFurquan Shaikh
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init() since it is included only in ramstage. Also, the content of ramstage_ec_init() is moved into mainboard_ec_init(). Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop mainboard_ec_init() from romstageFurquan Shaikh
mainboard_ec_init() does nothing in any stage other than ramstage. So, this change drops the call to mainboard_ec_init() from romstage.c. Additionally, it also drops ec.c from romstage and verstage. Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop unused function variant_romstage_entry()Furquan Shaikh
This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Use SSDT generator for Chrome EC audio codec deviceFurquan Shaikh
This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/kahlee: Drop macro H1_PCH_INTFurquan Shaikh
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-05mb/supermicro/x9scl: Select IPMI_KCSAngel Pons
Needed for `chip drivers/ipmi` in the devicetree. Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41687 Reviewed-by: Michael Niewöhner Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/lenovo/x230s: Add MAINBOARD_HAS_LPC_TPMKyösti Mälkki
With devicetree listing drivers/pc80/tpm, it is compulsory to have the corresponding driver included in the build. Followup work will drop the associated weak function declaration that util/sconfig currently generates. Change-Id: Ife8deb2c973ab7c7b820244b6f72efd3b56570ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/poppy-nocturne: Add SX9310 driver unconditionallyKyösti Mälkki
Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41726 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/volteer: Enable CSE Lite SKU for ES2 platformsJamie Ryu
BUG=b:158140797 TEST=build and boot volteer with CSE Lite SKU Cq-Depend: chrome-internal:3100721 Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42070 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/zork: adjust eSPI virtual irq settingsAaron Durbin
The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03mb/intel/cannonlake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41706 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/coffeelake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41705 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPIKyösti Mälkki
Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in WyvernEdward O'Callaghan
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in NoibatEdward O'Callaghan
BUG=b:160296662 BRANCH=none TEST=none Change-Id: I5298e1779461995a98722099b397692351767089 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in FaffyEdward O'Callaghan
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in KaisaEdward O'Callaghan
BUG=b:160296661 BRANCH=none TEST=none Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in DuffyEdward O'Callaghan
BUG=b:160296325 BRANCH=none TEST=none Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/pcengines/apu1/mainboard.c: reorder includesPiotr Kleinschmidt
Originally, there was problem with PC Engines apu1 platform which returned serial number value as -64. It was caused by wrong value of dev->bus->secondary. Source of the problem is in Porting.h header file. It contains '#pragma pack(1)' which affects struct device. As mainboard.c uses different binary layout because of this attribute, reference dev->bus->secondary lands at wrong memory address. This patch reorder includes and put <AGESA.h> and <AMD.h> at the end of list, making struct device consistent. As a result bus number value in device's structure is correct and hence serial number. TEST=`dmidecode -t 2` command in Linux Debian Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42512 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/zork: Generate I2SM ACPI device at runtimeFurquan Shaikh
This change moves the generation of I2SM ACPI device from static asl file to runtime generation by ACP device driver. dmic_select_gpio is set to match version 3+ of Trembyle and Dalboz schematics. In order to maintain backward compatibility, dmic_select_gpio is updated at runtime using variant_audio_update for board versions that are prior to version 3 of reference schematics. The only difference from static generation is that the device I2SM is added under ACPD (i.e. ACP device) instead of CREC (Chrome EC device). It does not make any functional difference from the kernel perspective. BUG=b:157603026 TEST=Verified that the following device gets generated in SSDT: Scope (\_SB.PCI0.PBRA.ACPD) { Device (I2SM) { Name (_HID, "AMDI5682") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "I2S machine driver") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x000D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "dmic-gpios", Package (0x04) { \_SB.PCI0.PBRA.ACPD.I2SM, Zero, Zero, Zero } } } }) } } Verified audio via speakers and mic input. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253638 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02mb/ocp: remove sonorapassJonathan Zhang
Sonora Pass server program was terminated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/faffy: update DPTF parametersTim Chen
Modify DPTF parameters for faffy from thermal team. BUG=b:160292247 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage verify the parameters are correct Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-01mb/google/zork: Move EC wake to happen in ramstageFurquan Shaikh
Currently, EC wake signal (GPIO_24) is configured early on in romstage. However, there is no need for that since EC wake is not really required to be configured until ramstage. This change moves GPIO_24 configuration to happen in ramstage. BUG=b:159832123 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/zork: Fix pad configurations for wake signalsFurquan Shaikh
This change updates the pad configurations for wake lines as follows: 1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake using GPIO controller block. This is because pen eject signal is not dual routed and the trigger filtering is set by the kernel driver differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and instead has to fall back to using GPIO controller wake. 2. All other wake signals (EC, trackpad, fingerprint) need to be configured as SCI. This allows OS to enable/disable wake from these sources if required. Example: powerd disables wake from trackpad when in tablet mode. Hence, all other wake sources use SCI. BUG=b:159832123 TEST=Verified wake using pen eject and EC. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/dedede: set tcc_offset value to 10Sumeet R Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/zork/var/morphius: Enable support for garaged stylusFurquan Shaikh
This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for morphius. BUG=b:158814699,b:158719244 Change-Id: I3530a0aa83ec69559436687205c64524b862799b Signed-off-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Drop unused/unnecessary GPIO macrosFurquan Shaikh
This change drops macros for GPIOs which are unused or don't really require extra indirection (same across all variants). BUG=b:159283649 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork/var/ezkinil: Fix GPIO_86 configuration for bid3Furquan Shaikh
Board version 3 for Ezkinil follows Trembyle reference v3.51 schematics and hence GPIO_86 does not need a variant specific override. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/42940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Drop GPIO_27 configuration for trembyle referenceFurquan Shaikh
This change drops GPIO_27 configuration for trembyle reference boards since it is unused. BUG=b:159453643 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I57dd78e8abcc61802ca85158e7ff348460ad1d8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Add support for active low wifi power enableFurquan Shaikh
A late change went into v3+ of reference schematics which inverted EN_PWR_WIFI to meet PCIe reset/power timings for WiFi device. This is incorporated into v3.51+ for Trembyle reference and v3.2+ for Dalboz reference. However, some variants are built with v3+ reference schematics, but without the inversion of EN_PWR_WIFI polarity. Thus, we need to add support for following combinations: 1. Pre-v3 Schematics 2. V3+ Schematics 3. V3+ Schematics + Active low wifi power This change adds a new Kconfig `VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW` that sets the minimum board ID that has EN_PWR_WIFI active low in hardware. Variants that missed this change in V3+ integration (berknip and vilboz) have board IDs set to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS + 1. For others, this defaults to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS. BUG=b:159749536 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Move GPIO sleep table to dalboz and trembyle referenceFurquan Shaikh
This change moves variant_sleep_gpio_table() definition to dalboz and trembyle references to allow each to make their own changes. BUG=b:159749536, b:159453643 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I15b19cea05f1a540c56b6bc0507306d2348ac17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalbozFurquan Shaikh
This change moves PCIE_RST1_L deassertion to happen as part of variant_pcie_power_reset_configure() instead of variant_romstage_entry() since romstage is guaranteed to run 100ms+ after PP3300_NVME is enabled. This is one of the first things that coreboot on x86 does as part of early mainboard configuration. Additionally, this change also drops deassertion of PCIE_RST0_L on bid 1 for dalboz since PCIE_RST0_L is already deasserted much earlier in the boot flow. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Configure GPIO_40 as drive low in sleep pathFurquan Shaikh
This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in sleep path so that the PERST# to NVMe device keeps asserted until coreboot reconfigures it as high on S3 resume path. This is similar to the earlier change for PCIE_RST1_L but helps platforms that use NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain, hence it retains state across S3 entry/exit. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep pathFurquan Shaikh
This change configures PCIE_RST1_L as GPO driven low on the sleep path. This is required to keep PERST# asserted to devices until coreboot deasserts it on S3 resume path. Without this change, on S3 resume, PCIE_RST1_L gets deasserted sooner than required resulting in violation of PCIe reset timings. With this change, the behavior of PCIE_RST1_L is as follows: 1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot bootblock/romstage and driven high. 2. On S3 entry, GPIO27 is configured as GPO driven low. * Boot out of G3: Timing should be met since GPIO_27 is pulled down by default until coreboot configures it. * S3 resume: Timing should be met since GPIO_27 is configured as GPO low and it retains state across S3 entry/exit. So, should be low until coreboot configures it. * Warm reset: Timing should be met since it is configured as NF. So, hardware guarantees the reset timing as seen in "warm reset.jpg" in #46. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261116 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Turn off power to camera and pen in sleep pathFurquan Shaikh
This change turns off power to camera and pen devices when entering sleep since they do not act as wake sources in S3. Power to trackpad and WiFi is left enabled since they are wake sources for S3. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I21bcdd53370372c7d43c3b685abb2a9171e42d22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261115 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Add support for GPIO configuration on sleep pathFurquan Shaikh
This change adds support to configure GPIOs on the sleep path. This is required to turn off power to devices that do not act as wake sources and to assert reset to devices. Currently, variant_sleep_gpio_table() returns an empty table by default. In the following changes, entries will be added to gpio_sleep_table. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253642 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/nightfury: Override VBT selection for nightfury 2nd skuSeunghwan Kim
Override VBT for nightfury SKU_ID = 2 to support different panel. BUG=b:159051021 BRANCH=firmware-hatch-12672.B TEST=Built and verified using different VBT by SKU_ID Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-01mb/google/zork: update G2 TS RST delay timeKevin Chiu
in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-01mb/prodrive/hermes/variants/baseboard: configure sataHotplugJonas Loeffelholz
Configure sataHotPlug in devicetree, as this functionality is now available for this soc. Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42804 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01mb/google/octopus/variants/dood: fix disable_xhci_lfps_pm by skuKenneth Chan
due to overridetree.cb set disable_xhci_lfps_pm = 0, need correct condition expression to let function work. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/42860 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO ↵Furquan Shaikh
configuration table Currently, for Stoneyridge and Picasso mainboards, pads that are configured for SCI/SMI/WAKE need to have multiple entries in the configuration table - one for PAD_GPI and other for the special configuration that is required. This requires a very specific ordering of pads within the table and is prone to errors because of conflicting params provided to the different entries for the same pad. This also does not work very well with the concept of override GPIOs where the entry in base table is overridden with the first matched entry from the override table. This change updates the way GPIO configuration is handled for special routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of soc_amd_gpio structure in the macros performing these configurations. Also, program_gpios() is updated to perform a write to GPIO control register instead of read-modify-write. This is because mainboard is expected to provide only a single configuration entry for each pad within a given table. Thus, there is no need to preserve earlier configuration. Mainboards that were providing multiple entries for a single pad are updated accordingly. BUG=b:159944426 Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODLFurquan Shaikh
H1 is not a wake source and hence there is no need to configure SCI GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9 i.e. H1_PCH_INT_ODL. BUG=b:159944426 Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30mb/amd/padmelon: Drop SCI configuration for GPIO_137Furquan Shaikh
GPIO_137 does not have any gevent associated with it. This change drops the configuration of GPIO_137 as SCI for padmelon. Change-Id: I0579d05bda4523bbb5e3441d2a3b6e2b33b05cfc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42873 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dtEdward O'Callaghan
BUG=b:159187889 BRANCH=none TEST=none Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-30mb/google/volteer: set tcc_offset value to 10Sumeet R Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 00:35:36 +0000