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This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb.
Reason for revert: broke the build
Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44993
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the Lindar's schematic, generate memory settings.
BUG=b:161089195
TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex".
2. Add SPD support in Rammus memory table, as follows:
SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110
SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111
BUG=b:166576463
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TPM2 set to yes by MAINBOARD_HAS_TPM2 at security/tpm/Kconfig file.
Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file.
Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig
Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10
BUG=b:162891673
BRANCH=kukui
TEST=make
Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
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'CONSOLE_SERIAL' is already set to 'y' at src/console/Kconfig.
Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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1. Apply the DPTF parameters receive from the thermal team.
2. Change PL2 min value from 25W to 15W.
3. Change PL2 max value from 64W to 51W.
BUG=b:166696500
BRANCH=puff
TEST=build and verify by thermal team
Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
BUG=b:158986928
BRANCH=puff
TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Relative path to spd directory was wrong.
BUG=b:167175547
TEST=Boot Trembyle SKU 2
Change-Id: I63ae4f39ba69d2d80c25ac7383b6eb953901f56d
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means
enable operation and 0 means stop operation. Override tree exposes
this pin as stop GPIO. Thus, it needs to be configured as active low
i.e. 0 = active (stop), 1 = inactive (enable report).
Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
Offset Current value Updated value Analysis
1 0x10 0x11 As per SPD spec rev 1.1
5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs
6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix
12 0x02 0x0A 2 ranks per ch, 16 bits device data width
18 0x05 0x04 4267MHz support
29 0x90 0xC0 HW specific
30 0x06 0x68 HW specific
31 0xD0 0x60 HW specific
32 0x02 0x04 HW specific
125 0x00 0xE1 4267MHz support
BUG=b:159319534
TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:155002684
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Checked with the schematics that all PCIe clocks have a corresponding
clock enable pin.
BUG=b:149970243
BRANCH=zork
Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:149970243
BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:149970243
BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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dirinboz does not support stylus, config AGPIO4/5 to NC
to prevent unexpected wake event for s3.
BUG=none
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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berknip does not support stylus, config AGPIO4/5 to NC
to prevent unexpected wake event for s3.
BUG=b:162376046
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I8d9b711ce1d7300181fe496d490dd33b38bc5983
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some Linux kernel drivers bind to "DMI quirks." In this case, the audio
fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S"
so the audio topology can be correctly discovered.
But add all successfully probed fw_config items as well, because this
makes it easier to view what is selected from userspace.
BUG=b:161963281
TEST=With CBI FW_CONFIG field set to 0x201:
localhost ~ # dmidecode -t 11
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: DB_USB-USB4_GEN2
String 2: AUDIO-MAX98373_ALC5682I_I2S
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I21378acd6408a4fae5600a54a41f695e54221dc2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44829
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibc2446d7b8d4334e26ca6335179f50b7abe301cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44831
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_F11 was in the early gpio table, but the definition was missing
from the main gpio_table. This change adds GPP_F11 to the gpio_table
array.
BUG=none
TEST="emerge-volteer coreboot" and verify it builds correctly.
Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Add Makefile.inc to include six generic DDR4 SPDs for the following
parts for Eldrid:
DRAM Part Name DRAM ID to assign
H5AN8G6NDJR-XNC 0 (0000)
MT40A512M16TB-062E:J 1 (0001)
H5ANAG6NCMR-XNC 2 (0010)
K4A8G165WC-BCWE 0 (0000)
K4AAG165WA-BCWE 3 (0011)
MT40A1G16KD-062E:E 3 (0011)
Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use
by gen_spd, the generic DD4 SPD generation tool.
Add dram_id_generated.txt to specify DRAM ID strap settings.
NOTE that Eldrid specified DRAM IDs for the first three parts to be 0
though 2 (i.e. no combined DRAM IDs for parts that use the same SPD).
BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
without error.
Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4c7f23615bcfd9c2bda2cac8808544b98f8e25a2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable TBT2 setting in overridetree.cb based on schematic.
BUG=b:165175296, b:166060548
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Set tcc offset to 5 degree celsius for kaisa and duffy
BUG=b:166696500
BRANCH=puff
TEST=Build, and verify test result by thermal team.
Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor.
When there is no M.2 card populated, the pin is floating. Thus
enable an internal 20K PD.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Add CNVi and PCIe wifi devices to the devicetree and enable the wifi
driver and SMBIOS tables in Kconfig.
Test: both CNVi and PCIe wifi devices work fine
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework the comments:
- fix wrong gpio / net names
- convert all comments to <gpio> / <net name>
- add more information where appropriate
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent
PAD_CFG_GPO.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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INTP_OUT can be used as Type-C VBUS sense input/interrupt but is
currently unused in coreboot. It isn't a requirement for PD to work.
Disable it for now.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable internal pull-ups for SATAXPCIE pads since there are external
ones at the M.2 slot's PEDET pins.
Test: both, SATA and NVME devices work fine on both slots
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are pads being unused for various reasons:
a) missing board support (DeepSx: SUSWARN#)
b) unneeded feature ID pins
- currently no known device models without keyboard backlight
- currently no known device models without TPM
c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time
d) DDR_TYPE_*: there is only one known ram model
e) strap-only pads
f) unconnected pads
Configure them as NC with appropriate pull-up if no external pull exists.
The latter was checked by schematics and looking at the board.
When any of the unused ID pins is needed in the future, they can be
reactivated easily (configure as GPI).
Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support CSE Lite firmware update, CSE RW partition is extracted from
CSE blob binary and added to FW_MAIN_A and FW_MAIN_B.
CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and
FW_MAIN_B is increased to avoid an overflow.
BUG=b:140448618
TEST=build with me_rw binary blob for volteer and boot to kernel.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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L140CU has a TPM2 connected via SPI. Add the TPM device to the
devicetree and enable it.
According to Intel doc#615170-001, PIRQ is required for SPI TPM to work.
Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as
TPM interrupt in Kconfig.
Note: The PCH maps either LPC TPM or SPI TPM to the same address and
handles either LPC or SPI communication transparently. Thus we can use
MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address.
Tested, but only polling works currently, because there is some upstream
issue with the tpm_tis module in current Linux kernels. [1]
[1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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burnet/esche
Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB
BUG=b:165956924
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence
to be active low.
BUG=b:160126287
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting
BUG=b:162302027
Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=woomax
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611555
TEST=none
Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These parts have not been used in any berknip devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=berknip
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611704
TEST=none
Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parts have not been used in any dirinboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=dirinboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611271
TEST=none
Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mem_list_variant.txt, a list of memory parts used by elemi SKUs.
Add dram_id.generated.txt, a list of dram id's to use for each memory part.
Add Makefile.inc, to specify DDR4 and build the SPD file list.
BUG=b:165461530
TEST=none
Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add memory parts needed by zork boards. Attributes are derived from data
sheets.
BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.
$ go run ./util/spd_tools/lp4x/gen_part_id.go \
src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt
Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.
This change updates that discrepancy in Delbin's memory Makefile.inc.
BUG=none
TEST=none
Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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