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2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Modify DQ/DQS mappingMike M Hsieh
Modify DQ Byte Map and DQS Byte Swizzling to match up with design BUG=chrome-os-partner:44647 BRANCH=none TEST=System boot up and pass memory initialization Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78 Original-Reviewed-on: https://chromium-review.googlesource.com/295518 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Clean up devicetree.cbDuncan Laurie
Fix the PCI device list comments to be consistent between mainboards and remove unused and incorrect register settings. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8 Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297339 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11562 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Clean up devicetree.cbDuncan Laurie
Clean up the PCI device list comments to be consistent between the skylake mainboards. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0080ab21db006365f34995db06480dae68ac547d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297338 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11561 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08sklrvp: Clean up devicetree.cbDuncan Laurie
Remove devicetree.cb settings that do not apply to skylake so they can be removed from chip.h and clean up the pci device comments and add missing devices. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509 Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297337 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11560 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the kunimitsu build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5 Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296302 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11554 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the glados build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-glados coreboot Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2 Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11553 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296036 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11548 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Update 4GB DIMM SPD for 1866Duncan Laurie
Enable 1866 timings in the 4GB Hynix SPD. BUG=chrome-os-partner:44394 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423 Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295174 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11528 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07intel: Do not hardcode the position of mrc.cacheAlexandru Gagniuc
The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-05amd/thatcher: include .c files with the right pathAaron Durbin
The #include path during compilation already has '-I src'. Don't encode the src part of a path. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built amd/thatcher while compiling romstage.c with C compiler.. Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11512 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-04mc_tcu3: Adjust gpio settingsWerner Zeh
Adjust gpio settings due to hardware change. Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11489 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-03mc_tcu3: Extend hwinfo.hex and remove version.hex.Werner Zeh
1. Update hwinfo.hex (add dummy data and update checksums). 2. Delete version.hex from mainboard directory. It can be added in site-local if needed. Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-31AMD bettong: Fix the PCIe lane mapzbao
Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31AMD Bettong: Set the USB3 port as unremoveable.zbao
Without this change, if one USB3 device is attached when the board is power up, the USB3 port can not be used. Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-30Kconfig: Don't 'select' options based on PAYLOAD_SEABIOSAlexandru Gagniuc
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11293 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2015-08-29intel/kunimitsu: Export EC_IN_RW for depthcharge/vbootzhuo-hao
Reference CL:294712 BUG=chrome-os-partner:43072,chrome-os-partner:43707 BRANCH=none TEST=build coreboot and boot on Kunimitsu Fab3.1 Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92 Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295514 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: port the change from glados for correctly reading lidrobbie zhang
switch and SPI write protect for fill_lb_gpios() to coreboot table. BUG=chrome-os-partner:43707 BRANCH=none TEST=build and boot on kunimits Signed-off-by: robbie zhang <robbie.zhang@intel.com> Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680 Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5 Original-Reviewed-on: https://chromium-review.googlesource.com/295580 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Remove unnecessary check for mainboard_ec_init()Martin Roth
mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: port the change from glados for enabling readingrobbie zhang
recovery mode. BUG=chrome-os-partner:43683 BRANCH=none TEST=build and boot on kunimits and successfully enter recovery mode by pressing “Esc + refresh + Power” keys. Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61 Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295138 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11434 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: Adding mainboard init to enable SCI eventpchandri
BUG=chrome-os-partner:44470 BRANCH=None TEST=Builds and Boots on FAB3 (Kunimitsu) Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8 Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295218 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: fix SCI handlingWenkai Du
Ported below patch from glados to kunimitsu: glados: Abstract board GPIO configuration in gpio.h Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Originally-signed-off-by: Duncan Laurie <dlaurie@chromium.org> Originally-reviewed-on: https://chromium-review.googlesource.com/293942 BUG=chrome-os-partner:40828 BRANCH=none TEST=Verify that acpi interrupts are incrementing on kunimitsu. Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295048 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11432 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: fix kepler probingWenkai Du
The patch was ported from commit: glados: fix kepler probing BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted kunimitsu. lscpi shows the device on bus 2. Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Originally-signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810 Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11431 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: Enable and support for DPTFShilpa Sreeramalu
This patch includes the DPTF specific ASL files in the main DSDT definition and enables the CPU thermal participant device in the device tree. It also enables the DPTF flag in the global NVS table.It also adds the ASL settings specfic to the mainboard. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284821 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294650 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11429 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: clean up ec smi and make EC_SMI_L functionalrobbie zhang
forward port of "glados: make EC_SMI_L functional", commit 50ed38feba58f BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08 Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295045 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11428 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/sklrvp: Switch to using GPIO IRQ definesDuncan Laurie
Use the macro for GPP_E22_IRQ instead of the ACPI code so it can be removed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5 Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295171 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/kunimitsu: do gpio configuration in coreboot instead of fsprobbie zhang
BUG=chrome-os-partner:44336 BRANCH=None TEST=Built and booted kunimitsu. Validation shows no regressions. CQ-DEPEND=CL:294757 Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295012 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11425 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-29intel/kunimitsu: add WP to gpio tableWenkai Du
This is needed to fix error in depthcharge: src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up for flag 3. BUG=chrome-os-partner:44214 TEST=Verify depthcharge prints EC ID on boot up BRANCH=None Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3 Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: configure gpio pads prior to SiliconInit()Aaron Durbin
Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11420 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: fix kepler probingAaron Durbin
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Export GPIO for EC_IN_RWDuncan Laurie
Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28veyron_rialto: remove spurious GPIO assignmentsAlexandru M Stan
GPIO(0, B, 3) and GPIO(7, C, 5) are not actually connected, GPIO(0, B, 4) is named differently. BUG=chrome-os-partner:43031 TEST=Rialto should still boot just fine, USB should still work BRANCH=master Change-Id: I11879385de6e9b57ac28bcae699333beb5a0d64c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a66bf1fd73ff8d15d4ec1a8f3602465941285c32 Original-Change-Id: Ib7d2baa6ed1ab38db786eb4d5e77316ad72cbfd4 Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294713 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: add Nanya NT5CC256M16DP sdramjinkun.hong
BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 Reviewed-on: http://review.coreboot.org/11399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron_rialto: Turn on all ledsAlexandru M Stan
Without this, the leds would be stuck to whatever the pullup/down states the pins come with on rk3288. Ready2_LED, an orange led, is one of the leds in this state. This might confuse some users thinking there's an error. Turn all of them on instead. Later on depthcharge will use the same LEDs to indicate dev mode status. BUG=chrome-os-partner:44274 BRANCH=master TEST=Boot firmware without anything else, note all leds on Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5 Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589 Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294065 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11398 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odtjinkun.hong
only modify the MR3 value, there will always be some mickey not working properly. After enable ODT, we use many mickey do tests, now functioning properly. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8 Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293324 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Original-Trybot-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf) Original-Reviewed-on: https://chromium-review.googlesource.com/294126 Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff Reviewed-on: http://review.coreboot.org/11396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 OhmDouglas Anderson
The value of 0x4 (60 Ohm) apperas to be causing lots of problems. Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and hope it's the sweet spot. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15 Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291121 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071) Original-Reviewed-on: https://chromium-review.googlesource.com/291291 Change-Id: Id32790c894c09616e32503aa790fa294093eca8a Reviewed-on: http://review.coreboot.org/11386 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28veyron_rialto: Force 3G modem offDavid Hendricks
This basically does the same thing for firmware what CL:290631 did in the kernel. We want to keep the modem off until it needs to be used to avoid enumeration/detection issues. BUG=chrome-os-partner:43271 BRANCH=none TEST=needs testing Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4 Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290890 Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-on: http://review.coreboot.org/11385 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28Smaug: Add NVDEC and TSEC carveoutsTom Warren
The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 Reviewed-on: http://review.coreboot.org/11381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27packardbell/ms2290/mainboard.c: Do not guard int15 includesAlexandru Gagniuc
Do not guard the inclusion of "drivers/intel/gma/int15.h" and "arch/interrupt.h" with configs that control option rom execution. These headers already have the proper guards. The install_intel_vga_int15_handler() is unconditionally called, even when the header that declares it is guarded out. Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11379 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UARTMartin Roth
This seems like more of a debug option, than something that should be forced to be enabled by the platform. Since it's causing a Kconfig warning, I'm just removing it. The alternative to removing it would be to add dependencies on CONSOLE_CBMEM && !CONSOLE_SERIAL Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11343 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-27skylake: FAB3 Adding Support for various SPD.pchandri
This pach enables memory configuration based on PCH_MEM_CFG and EC_BRD_ID. BRANCH=None BUG=chrome-os-partner:44087 CQ-DEPEND=CL:293832 TEST=Build and Boot FAB3 (Kunimitsu) Original-Change-Id: I7999e609c4b0b3c89a9689ee6bb6b98c88703809 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293787 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I52a1af1683b74e5cad71b9e4861942a23869f255 Signed-off-by: pchandri <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/11284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Abstract board GPIO configuration in gpio.hDuncan Laurie
Move all the various places that look at board specific GPIOs into the mainboard gpio.h so it can be easily ported to new boards. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Implement Chrome OS specific handlersDuncan Laurie
Implement the required Chrome OS specific handlers to read the recovery mode, clear the recovery mode, read the lid switch state, and read the write protect state using the appropriate methods. Also update the Chrome OS ACPI device to use the GPIO definitions that are exposed now by the SOC. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados and successfully enter recovery mode Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293515 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Fix SPD part number for Hynix H9CCNNN8JTBLARDuncan Laurie
The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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