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2013-07-16beaglebone: Get rid of a redundant CBFS_ROM_OFFSET.Gabe Black
CBFS_ROM_OFFSET was declared in both the am335x config and the beaglebone config. This removes it from the beaglebone config. Change-Id: I657cb8e83a1ee961d8bdc995a41f303920bc53f9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-07-16AMD Fam15tn: Split DSDT into common sectionsSteve Goodrich
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/3629 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-15beaglebone: Put some code in romstage.c so we can tell if it ran.Gabe Black
The placeholder code in beaglebone's romstage.c didn't do anything, it just immediately tried to load the RAM stage and jump into it. That doesn't currently work, and there's no indication whether you actually successfully got into the ROM stage or not. This change adds a few lines which initialize the console and say "Hi" so that we can tell that the ROM stage is running. Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14SMBIOS: Allow overriding default Manufacturer and Product namesPeter Stuge
The vendor and part name from coreboot is normally stored in these SMBIOS structure fields, but it can be useful to override them. On Lenovo ThinkPads an override is e.g. needed to convince the Linux thinkpad_acpi.c driver that it is actually running on a ThinkPad. Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-14lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVOPeter Stuge
This is needed for the Linux thinkpad_acpi.c driver to load. Change-Id: I3d9549395556ffb0abfc3cb52b3d01386c34caa5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3731 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-13lenovo/x60: Move mainboard_enable() code into a mainboard_init()Peter Stuge
mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: Iaf9187532a1e432b991260201b95dda85cc312c5 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Redo the display port bridge initialization code.Gabe Black
The display port bridge on pit is different from the one on snow and needs to be initialized differently. Instead of waiting for the chip to come up on its own and assert the hotplug detect, we need to access it over i2c and get it up and running ourselves. Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Enable the ps8625 driver.Gabe Black
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop setting up the hardware dp hotplug detect in ROM stage too.Gabe Black
This was removed from ramstage a little while ago and should have been removed from here as well. Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: add panel to the list of things to be powered up by the PMICRonald G. Minnich
This appears to be needed, though we have no way to test yet. Change-Id: I39033581011e056258193f2cdff78814361a8d55 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos: Prevent unexpected reboots in resume.Hung-Te Lin
In resume path, if memory setup takes too long without setting PS_HOLD, EC watch dog may power off or reboot the system. To prevent that, we should enable PS_HOLD in same timing as cold boot - right before starting memory setup. Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the tps65090 functions and adjust the hotplug detect line.Gabe Black
The functions which manipulated the tps65090 were removed a while ago because it isn't accessible directly from the AP, it's on an I2C bus that has to be accessed by the EC on our behalf. Now that that capability has been added, we can rewrite the small portion of the the tps65090 we actually used but using the EC passthrough commands. Also, we should not be configuring the hardware display port hotplug detect line since we're using it as a GPIO for other purposes. The GPIO we're using instead defaults to being an input, but to be safe we should probably explicitly configure it as one anyway. Change-Id: I7f8a8a767e3cccb813513940a5feceea482982f5 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Correct EC device in mainboard configuration.Hung-Te Lin
The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C. Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Setup EC on SPI2.Hung-Te Lin
The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: update I2C4 speed constantDavid Hendricks
Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Configure the pinmux for the i2c busses that are connected on pit.Gabe Black
Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554) Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5250: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Simplify early / bootblock console codeStefan Reinauer
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the snow GPIO indexes with ones for pit.Gabe Black
The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Remove the MAX_CPUS option.Gabe Black
The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop compiling in the max77686 driver on pit.Gabe Black
That part isn't used on pit. Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop calling tps65090 functions until we can call through the EC.Gabe Black
On pit, the tps65090 is connected to the EC and has to be accessed by proxy. Until we have that implemented, this change removes calls to tps69050 which will never succeed, and stops compiling in the driver. Change-Id: I7218f85f9f26623bd13aaaf8ded0638b3b2f874a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: set up the PMIC correctlyDavid Hendricks
This updates the setup_power() function to actually set up the PMIC which is on this board (the MAX77802). Change-Id: I9c6f21f183dacc0bca71277e681e670834412d78 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: memory setupRonald G. Minnich
Tested and working. Gets us to ramstage. Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Implement support for the pinmux as functions.Gabe Black
Change-Id: I5e0ec360597cd95cb6510fb32b04d8931e6a33db Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: De-switch-ify the pinmux configuration code.Gabe Black
The pinmux code for the exynos5250 was all bundled into a single, large function which contained a switch statement that would set up the pins for different peripherals within the SOC. There was also a "flags" parameter, the meaning of which, if any, depended on which peripheral was being set up. There are several problems with that approach. First, the code is inefficient in both time and space. The caller knows which peripheral it wants to set up, but that information is encoded in a constant which has to be unpacked within the function before any action can be taken. If there were a function per peripheral, that information would be implicit. Also, the compiler and linker are forced to include the entire function with all its cases even if most of them are never called. If each peripheral was a function, the unused ones could be garbage collected. Second, it would be possible to try to set up a peripheral which that function doesn't know about, so there has to be additional error checking/handling. If each peripheral had a function, the fact that there was a function to call at all would imply that the call would be understood. Third, the flags parameter is fairly opaque, usually doesn't do anything, and sometimes has to have multiple values embedded in it. By having separate functions, you can have only the parameters you actually want, give them names that make sense, and pass in values directly. Fourth, having one giant function pretends to be a generic, portable API, but in reality, the only way it's useful is to call it with constants which are specific to a particular implementation of that API. It's highly unlikely that a bit of code will need to set up a peripheral but have no idea what that peripheral actually is. Call sights for the prior pinmux API have been updated. Also, pinmux initialization within the i2c driver was moved to be in the board setup code where it really probably belongs. The function block that implements the I2C controller may be shared between multiple SOCs (and in fact is), and those SOCs may have different pinmuxes (which they do). Other places this same sort of change can be made are the pinmux code for the 5420, and the clock configuration code for both the 5250 and the 5420. Change-Id: Ie9133a895e0dd861cb06a6d5f995b8770b6dc8cf Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: Separate the early console (romstage) from the bootblock console.Gabe Black
It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10google/pit: Don't spew output with GPIO configStefan Reinauer
There are hundreds of GPIOs on the Exynos5420. Don't always print all of them per default. Change-Id: I2152ab760e31a335dbcd9d6ad32cd1eaae4b89bc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Simplify the graphics code by eliminating the unused color mapStefan Reinauer
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: I29bc17488539dbe695908e47f0b80c07e102e17d Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/3666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7: Reserve space BL1 and checksum header by specifying bootblock offset.Hung-Te Lin
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be different (ex, Exynos 5250 may use a new BL1 with variable length checksum header). To support that better, define the real base address (and ROM offset) of boot block, and then we can post-processing ROM image file by filling data / checksum and any other information. Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3664 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10google/snow: Don't spew output with GPIO configStefan Reinauer
There are hundreds of GPIOs on the Exynos5250. Don't always print all of them per default. Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3661 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10chrome ec: Update EC header from EC repositoryDuncan Laurie
- Updated ec_commands.h is copied in directly from EC repo - Removed "old" interface and update resources for "new" interface - Updated temp sensor constants and added "not calibrated" - Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Replace the 5250 clock logic with 5420.Gabe Black
The new code is stolen from U-Boot with little or no understanding of how it works. Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Clean up console codeStefan Reinauer
- Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I983d011c6ca602445f447d17799c1b2a33e8bd1d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Remove hardcoded GPI offset in EC SCIDuncan Laurie
With LynxPoint-LP the SCI GPE is no longer a GPIO that is offset by 16. Remove the Add and fix up the link definition so it is still accurate. Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: Simplify the graphics code by eliminating the unused color map.Gabe Black
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3652 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10snow: Make coreboot set up pins for busses it knows are hooked up as suchGabe Black
Coreboot knows that, for the snow board, certain pins are to be connected to bus controllers in the SOC and to the wires of a bus external to the SOC. It can configure them as such and free its payload from having to know how to set everything up. Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3650 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-07-10ARMv7: Clean up console codeStefan Reinauer
- Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock - Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Add a "pit" mainboard which is mostly a copy of "snow".Gabe Black
This change adds a pit mainboard which is mostly a copy of snow, except that mentions of the 5250 were replaced with the 5420, and mentions of snow were replaced with pit. Change-Id: I8eb0ce379eb2fa353bb88d5656a0c5e2290afbf0 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Create an exynos5420 directory which is nearly a copy of exynos5250.Gabe Black
This change creates an exynos5420 directory with code that will eventually implement support for the exynos5420 cpu from Samsung. Currently it's a copy of the exynos5250 directory with the name changed. There are going to be some problems where headers in src/cpu/samsung/exynos-common include headers in the exynos5250 directory directly. Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 GPIO codeStefan Reinauer
The Exynos GPIO code has three different APIs that, unfortunately, were widely used throughout the code base. This patch is cleaning up the mess. Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3643 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 codeStefan Reinauer
When starting the Exynos5250 port, a lot of unneeded u-boot code was imported. This is an attempt to get rid of a lot of unneeded code before the port is used as a basis for further ARM ports. There is a lot more that can be done, including cleaning up the 5250's Kconfig file. Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3642 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10samsung/exynos5250: unify codeStefan Reinauer
It turns out that the exynos5-common code previously imported from u-boot is not common code at all but very specific to the 5250 and not compatible with the 5450. Hence, unify the directories exynos5250 and exynos5-common. We will try to factor out common code while progressing with the 5450 port. Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3641 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Wield battle axe at ARM portStefan Reinauer
This patch unfortunately incorporates a number of changes, all of which are making future ARM ports easier. - drop cruft that came in with u-boot - move serial console from mainboard Kconfig to Exynos Kconfig - factor out non-board specific wakeup code - move generic bootblock code from mainboard to Exynos - actually call arch_cpu_init() - remove dead code - fix up copyright messages - remove snow_ prefix from a lot of code to reduce the noise when creating a new mainboard based on that code. Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3640 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: normalize ramstage code flowStefan Reinauer
In ram stage, all code flow should be tied to the resource allocator. Stuff that has to happen before everything else goes into the mainboard enable function in mainboard.c. This patch empties the main() wrapper around hardwaremain.c, allowing to get rid of this special case in the ARM port. Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10FUI: reorganize include filesRonald G. Minnich
We've got enough of a handle on this to realize some things: drm_dp_helper.h is by design device and architecture independent i915.h is common to most intel graphics chipsets going back several years i915_reg.h is as well Move these files to src/include/device, and adjust the .c files accordingly. Change-Id: I07512b3695fea0b22949074b467986420783d62a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3637 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Provide support for setting up the framebuffer from EDIDRonald G. Minnich
Add three functions to edid.c: void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr) takes an edid and uintptr_t, and fills in a static lb_framebuffer struct as well as setting the static vbe_valid to 1 unless some problem is found in the edid. The intent here is that this could be called from the native graphics setup code on both ARM and x86. int vbe_mode_info_valid(void) returns value of the static vbe_valid. void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) copies the static edid_fb to lb_framebuffer. There is now a common vbe.h in src/include, removed the two special ones. In general, graphics in coreboot is a mess, but graphics is always a mess. We don't have a clean way to try two different ways to turn on a device and use the one that works. One battle at a time. Overall, things are much better. The best part: this code would also work for ARM, which also uses EDID. Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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