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2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-09mohonpeak/Kconfig: Fix whitespace issuesMartin Roth
Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12655 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-09google/oak: define flash sizePatrick Georgi
We never defined the flash size for this board, so the (too small) default was used. Instead, adopt the size given in depthcharge's fmap description. Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12674 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-08intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside KconfigMartin Roth
The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when it was used in the C code. Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08lenovo/t500: Add clone of Lenovo T400Francis Rowe
The existing code for the Lenovo T400 works without changes on the Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08intel/littleplains: Update with recent changes to mohonpeakMartin Roth
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12635 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-07mainboard/asus/kgpe-d16: Use I/O PCI access in bootblockTimothy Pearson
The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12651 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-06pcengines/apu1: Supply _HID object for ACPI GPIO devicesMartin Roth
The _HID was present for the top level BTNS and LEDS Devices, but was missing in the individual devices. The alternative would be to supply the GPIO being used as an _ADR object, but since it looks like the driver already has another method of handling that, it isn't required. Fixes these IASL warnings: dsdt.aml 1522: Device (BTN1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1567: Device (LED1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1576: Device (LED2) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1587: Device (LED3) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12582 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/fsp_rangeley: change non-existent config options to #definesMartin Roth
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian <david.guckian@intel.com> Tested-by: build bot (Jenkins)
2015-12-06hp/pavilion_m6_1035dx: Fix IASL warning - Missing _HID objectMartin Roth
- Add System board _HID object. - Remove Kconfig default disabling IASL warnings as errors Fixes warning: dsdt.aml 64: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I4fa6ab2a6744d58ded8b0feb361e002d90e11474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06Rangeley: Change A, A, A, A INT routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12629 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/eagleheights: Fix IASL warningsMartin Roth
The eagleheights platform had 3 warnings: The SIO device needs an _ADR object to specify the address in addition to the operating region. Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. dsdt.aml 341: Device(SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 140: Method (_OSC, 4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 140: Method (_OSC, 4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) - Remove Kconfig default disabling IASL warnings as errors. Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04google/oak: Add timestamps in romstageYidi Lin
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04esd/atom15: import esd atom15 boardMichael Tasche
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8Michael Tasche
The E38xx legacy uart fires IRQ4, not IRQ3. PCI based IRQ A is switched from IRQ4 to IRQ3, to get a working IRQ for the legacy uart. Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744 Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12622 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-12-04mainboard/biostar/am1ml: Force basic SPI read modeSergej Ivanov
This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/12580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabiosMartin Roth
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/chell: update dptf TSR1 & TSR2 critial pointsWisley
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Coreboot GPIO changes for FAB 4.Saurabh Satija
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID, AUDIO_IRQ and BOOT_BEEP. BUG=chrome-os-partner:47513 BRANCH=none TEST=Built for kunimitsu but not verified on Fab 4. Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7 Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311806 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12600 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/lars: SPD change for Proto boarddavid
Update Memory ID for Proto board Update detection of single/dual channel memory to use SPD Index (Memory ID) Remove boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Build and Boot Lars (Proto) Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8 Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313903 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12593 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Updated Micron SPD dataBrandon Breitenstein
Updated Micron SPD data to correct values BUG=none BRANCH=none TEST=Tested on FAB 4 with Micron Dimm CQ-DEPEND=CL:312546 Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735 Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313003 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12592 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: FAB 4 update for Rcomp Target tableBrandon Breitenstein
Changed index 3 to be an exception of the default Rcomp Value BUG=None BRANCH=None TEST=Tested on FAB 4 SKU 1 Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622 Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/12591 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/Kunimitsu: FAB 4 SPD changesBrandon Breitenstein
Updated Memory IDs and SKU IDs for FAB 4 Updated detection of single/dual channel memory to use SPD Index (Memory ID) Added spd files for new dimms Removed boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Tested on FAB4 SKU1 and SKU3 Change-Id: I60403c0e636ea28797d94cff9431af921631323e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4 Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312546 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12590 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add a stub implementation of the MT8173 SoCYidi Lin
BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02lippert/frontronner-af & toucan-af: Fix IASL warningsMartin Roth
Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12530 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02mainboard/intel/d510mo: Add Intel D510MO mainboardDamien Zammit
Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-01mainboard/asus/kgpe-d16: Enable GART by defaultTimothy Pearson
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30mainboard/intel: Add Little PlainsMarcin Wojciechowski
This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHzTimothy Pearson
The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbolMartin Roth
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually existed in the coreboot codebase. I didn't see anything that it might have been a typo of. Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12563 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-27ibase/mb899: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Move Named objects out of _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes these items: dsdt.aml 1449: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1458: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I801a84468097687c91d6ee3f44cec06243355fac Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12531 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27kontron/986lcd-m: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning and remark: dsdt.aml 1451: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1460: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I4aa59468a89c4013146ab34004476a0968c60707 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12521 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-26mainboard/asus/kgpe-d16: Add missing IOMMU setupTimothy Pearson
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12527 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26mainboard/asus/kgpe-d16: Add IOMMU nvram configuration optionTimothy Pearson
Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24lenovo t400: Fix IASL warning and remarkMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably, the ATPX would not need a return value if Arg0 is anything other than 0, so just return a zero. - Serialize ATPX method to make IASL happy. This means that it can only be used by one thread at a time. Fixes these issues: dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Warning 3115 - ^ Not all control paths return a value (ATPX) Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12518 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24google/rambi: Fix IASL warnings _CRS must return a valueMartin Roth
The Touchpad and Touchscreen _CRS methods do not return an interrupt value if the I2c busses that the devices are on are not in PCI mode. Previously they didn't return any value if they weren't in PCI mode. This patch has them return an empty resource template. Fixes these warnings: dsdt.aml 2813: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2813: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) dsdt.aml 2832: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2832: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24iwave/IWRainBowG6: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning: dsdt.aml 1362: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Fixes IASL remark: dsdt.aml 1353: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24ec/lenovo/h8: Fix IASL warningsMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably the MKHP method wouldn't get called unless there were a pending event, but if no event is found, return a zero. Fixes IASL warning: dsdt.aml 1785: Method (MHKP, 0, NotSerialized) Warning 3115 - ^ Not all control paths return a value (MHKP) This was the only IASL warning in most lenovo mainboards. Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24superio/smsc/mec1308: Fix IASL warningsMartin Roth
The SIO device needs to provide an _ADR object with the IO address as well as the address in the OperationRegion. ACPI provides two different Resource Descriptor Macros to describe the I/O areas required for a device. The FixedIO macro is only valid for 10-bit IO addresses. Use the IO macro instead. Thank you to recent IASL that allows for addition in the ASL file. :) Fixes these warnings: dsdt.aml 2276: Device (SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 2390: FixedIO (0xa00, 0x34) Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF) dsdt.aml 2394: FixedIO (0xa00, 0x34) Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF) Lumpy now compiles its ASL tables with no warnings. Re-enable Warnings as errors. Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12520 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24intel/d945gclf: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors dsdt.aml 1445: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1454: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12523 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24AMD/bettong: Add UART supportZheng Bao
The function delay in uart8250mem.c is not enough for hudson. I guess there are some problems in lapic_timer(). I uploaded a patch to gerrit to show the way to enable UART feature. http://review.coreboot.org/#/c/12343/4 Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to enable this feature. The UART is test at BIOS stage. Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gartTimothy Pearson
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12046 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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