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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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These boards don't include any from sb/amd/sb800.
Change-Id: I2dbe39df6e4c5a86a0714b396bb89b03bbafd164
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36987
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add VBT file extracted from vendor (AMI) firmware,
use by default to ensure functional display after
resume from S3 when using libgfxinit.
Test: build/boot Librem 13v1/15v2 boards, verify
functional display after resume from S3 when using libgfxinit.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I44d75486da3083cd1f07ea82dc18688db84a621e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36916
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO49 is strapped high, so setting it low likely increases power
usage. GPIO53 is hooked to a testpad so there is no reason to set
it here.
Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Create new variant for jinlon
BUG=b:144150654
TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto
board
Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This also permits removal of vc/amd/agesa/f12, as it was the only
mainboard using it. That will in turn allow resolving some unique
Coverity issues reported against that source.
Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This board never really existed and nobody has any hardware left over
for it.
Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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By removing this code, we get approximately back to
where the board was before the fmap cache feature
was added, which is small enough for the Chromium OS
default configuration for the board to fit into the
32KB that the bootblock can use on the chipset again.
Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid
probing by the MRC. We can do that for all boards instead, based on the
devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The integrated GbE port is toggled via the Backed-Up Control (BUC)
register. We already disable it according to the devicetree setting
but never enabled it. This could lead to the confusing situation
that it was disabled before (different build, vendor BIOS, etc.)
but shouldn't be anymore.
As we need a full reset after enabling GbE, do it in early PCH init.
Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This is supported by generic PCH code now.
Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Don't overwrite the LPC decode config of the generic PCH code, move
UART init into bootblock_mainboard_early_init() and don't enable the
IOAPIC, which is already done by generic code.
Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move UART initialization to bootblock_mainboard_early_init() and don't
override the generic LPC decode settings.
Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The BUC register is actually 8 bits wide and shouldn't be bluntly
cleared.
Change-Id: I2ffd2d161005e839e730102b56af4f66efeb551e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Only set LPC decode bits that the generic PCH code doesn't set yet. And
don't enable the IOAPIC, which is already done by generic code.
Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This bit is already cleared by a reset.
Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This bit is used to indicate xHCI routing across reboots. If anything,
coreboot should act on it, not set it during boot. ASL code would be
supposed to set it.
Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The generic PCH code already enables a superset of LPC decoding. Move
UART setup to bootblock_mainboard_early_init() where it is expected.
Last but not least, remove an odd write to BUCs (RCBA+0x3414) and
beyond, as it's an 8-bit register and shouldn't be bluntly zeroed.
Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The generic PCH code already sets up a superset of these decodings.
Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4
things here on top of the generic PCH code:
1. Enabling LPC decoding for gameports. It seems unlikely
that anything is using these ports and there is no code
to support gameports.
2. Decoding of COM3 instead of COM2. What COM?
3. Premature locking of ETR3/global reset. Bad idea.
4. Disabling the GbE port in BUC. Already done by PCH code.
Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This also changes the name to mainboard_late_rcba_config to better
reflect what it does.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This adds an empty weakly linked default. The rationale behind this
change is that without the callback some features might not work
but that the result is likely still able to boot, so it can be made
optional.
Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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RCBA32(V0CTL)= 0x80000001 already done inhere i945/early_init.c
Change-Id: Ia775f4e6158a217b48629d289845537e7ccf5e79
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Setting GPP_A10 to NC now that older boards are deprecated and this
GPIO is not in use anymore.
BUG=b:142056166
BRANCH=hatch
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These mainboard don't feature a SPI flash. The SPI init code
will timeout on probing for a SPI flash which takes a lot of time.
Not including all SPI drivers also lightens the uncompressed ramstage
of about 17K or 7K compressed.
Change-Id: Icc7bf62d56fc2ef38854402e658830b8d59c737f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36870
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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This adds callbacks for mainboard specific init.
Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds 3 mb romstage callbacks:
- void mb_lpc_setup(void) to be used to set up the superio
- void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs
- (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard
specific things before the raminit.
Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add IFD and ME binary to generate complete SPI image.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34448
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new Kukui follower 'kakadu'.
BUG=None
TEST=make # select kakadu
Change-Id: I9f25ce90285828c43435e45d9361ee7128d407fa
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36848
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add semtech SAR sensor.
BUG=b:143449140
BRANCH=octopus
TEST=Boot kernel with sx931x driver, i2cdetect show UU on slave address.
Change-Id: Icfb8acf1bac73973748aa7443c95147c60bad770
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36850
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:144327240
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I68b71425391eda1e92806fecdb9c8dcd54f0b95a
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36771
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the logo.bmp file from the verify list when FSP1_1_DISPLAY_LOGO
is not set.
BUG=N/A
TEST=build
Change-Id: I87eac0b3cbe9450d5623b5331d8de096f140b595
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36853
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Changed the order of the verify lists and updated the comments to
reflect the order of execution. This makes the list easier to understand
and maintain.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Ia656fbf07e5d42bafd328eaba69b660e5a1e4f1a
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36817
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change from hardcoded "fallback/*" to using CONFIG_CBFS_PREFIX.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Ie728d01ebb93edd88516e91528ecaaa3f139b7a9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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The public key should only be validated if the manifest is signed.
BUG=N/A
TEST=testedd on fbg1701
Change-Id: I703ed442e0b1926859f593ce9ca84133013224ea
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Removed unused include file.
BUG=N/A
TEST=build
Change-Id: I040b695a893b51de06f9658abdca8867727f053d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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The postcar_verify_list should contain the items that should be verified
before the postcar stage is started.
BUG=N/A
TEST=build
Change-Id: I328858e4803873fed6d47313def5e7b9a434e8ad
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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The bootblock measurement was handled using the romstage_verify_list()
and the public_key in the mb_log_list. This is confusing as these are
both read-only items that should be handled in the same way.
Both will be handled in the romstage_verify_list().
BUG=N/A
TEST=tested on fbg1701
Change-Id: If05198deec85188f39a221a8b755798755afa5bb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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vb2_context object is now stored on the workbuf as part of
vb2_shared_data. Use vboot's new API functions vb2api_init
and vb2api_relocate to create and move the workbuf.
BUG=b:124141368, chromium:994060
TEST=Build locally
BRANCH=none
Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa
Signed-off-by: Joel Kitching <kitching@google.com>
Also-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1902339
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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