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2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20mb/google/dedede: Update link frequency and end point structure for OV9734Pandya, Varshit B
1. Update Link frequency to 180 Mhz 2. Set data-lanes to 1 and 3. Update the clock-lane used by sensor BUG=b:155285666 BRANCH=None TEST=Build and able to capture image using user facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20mb/amd/mandolin: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for dalboz referenceFurquan Shaikh
This change drops internal pulls for dalboz reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP1800_S0 GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_32: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for trembyle referenceFurquan Shaikh
This change drops internal pulls for trembyle reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP3300_A GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_90: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-20mb/asrock/b85m_pro4: Enable VGA portAngel Pons
Now that libgfxinit has been fixed, trying to enable the Analog port no longer hangs the system, nor fills the monitor with unreadable garbage. Tested with linear framebuffer, displays correctly on a 1920x1080 VGA monitor. Scaling also works when a smaller HDMI monitor is connected as well. Legacy VGA text mode is also functional on either monitor, too. Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19mb/qemu-i440fx/memmap: Add warning when falling back to CMOS infosNico Huber
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Fix return code check for fw_cfg_e820_select()Nico Huber
Change-Id: I22b9eb6ead37dbba6807d145468843bd01c94c84 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Add info messages about (not) found filesNico Huber
Print some more information at BIOS_INFO, like our CBFS code does. Change-Id: I1431d569c57634277ea5cf7feb352419db432b44 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43444 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/volteer: Update DPTF with temp sensor 3Tim Wawrzynczak
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those. BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-17mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine deviceFurquan Shaikh
Vilboz requires a different HID than rest of the zork variants. Hence, this change sets the HID to AMDI1015 for I2S machine device in vilboz overridetree.cb. BUG=b:157708581 Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Switch to using newly added i2s_machine_dev driverFurquan Shaikh
This change switches zork devices to use the newly added i2s_machine_dev driver in devicetree rather than passing dmic_select_gpio in SoC config. BUG=b:157708581 Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17mb/asrock/b85m_pro4: Select MAINBOARD_USES_IFD_GBE_REGIONAngel Pons
This board uses the in-PCH GbE controller, and its IFD has a GbE region. Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/amd/mandolin: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: correct wake gpe value for gpio 9Aaron Durbin
GPIO_9 is associated with gevent 22. Correct all the misconfigurations and use macros for clarity as to what bit offset is being used instead of open coding things. BUG=b:161205804 Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_ENFurquan Shaikh
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle boards using devicetree settings. BUG=b:161328042,b:146317284 Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUsFelix Held
Dali supports two SATA ports, but no PCIe alternate function on those pins. Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/amd/mandolin: fix DXIO lane numbersFelix Held
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/amd/mandolin/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/google/zork: Move variant_pcie_gpio_configure() to bootblockFurquan Shaikh
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop redundant romstage GPIO tableFurquan Shaikh
Now that the power and reset GPIO configuration for non-PCIe devices is dropped from romstage GPIO table, the tables for pre-v3 and v3 version of schematics are exactly same. So, this change drops the duplicate table and also removes the check for v3 schematics when configuring the pads in romstage. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for dalbozFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage for dalboz reference as this is not required. +---------------------------------------------------------------------------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 6 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | | | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 141 | USB_HUB_RST_L | 10K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for trembyleFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage as this is not required. +---------------------+--------------------------------------------+--------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 13 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | |_PS2 | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | | | | | | | | | +-----+---------------+---------+---------+-------+----------------+--------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ieadc62f1a13857209cf0a62f204efb9278e0e97d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Keep USI_RST asserted in ramstageFurquan Shaikh
This change keeps USI_RST(GPIO_140) asserted in ramstage since it gets deasserted by OS using ACPI methods. BUG=b:160854397 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I8feced788e471a0efb2358d42b2146df04fb7a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43461 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Keep pen power enabled in sleep stateFurquan Shaikh
This change keeps pen power enabled in sleep state to allow it to charge in S3. BUG=b:155422911 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6190496653878327f34a01f6a743db474d32e929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"Philipp Deppenwiese
This reverts commit a5ca4a0c75237093f1a4d90f30c0c932e5fcd05d. Reason for revert: Breaks coreboot tree because of non existent kconfig symbol Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/ocp/deltalake: Select IPMI OCP to send POST start/end commandTimChu
Implement sending POST start/end command to BMC. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST Start Event for Payload#1 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST End Event for Payload#1 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-16mb/google/kukui: Add new config 'willow'Sheng-Liang Pan
New board introduced to Kukui family. BUG=b:159194582 TEST=None BRANCH=kukui Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Icc6bcbd006008a05303693e481a54636f0645887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16google/trogdor: Remove GPIO_AP_SUSPEND_LJulius Werner
This pin has been removed from recent revisions (or at least moved to a pin that's not controlled like a normal GPIO). It has also never been used on older ones (I think?). The same GPIO is now used as a SKU ID pin, so make sure we're not incorrectly configuring it as an output (although sku_id() overrides that later anyway, but it's still incorrect). BUG=b:160754995 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Remove redundant PCI info from overridetreesRob Barnes
This information is redundant since it's already specified in baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb domain 0 is still required because sconfig uses it as an identity anchor to match devicetree and overridetree. BUG=b:157580724 TEST=Boot zork, usb functional Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/dedede: Enable SIS touchscreen for WaddledeeKarthikeyan Ramasubramanian
Add SiS9813 USI touchscreen support. BUG=b:160129126 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/volteer: Enable SATA Port Dito ConfigShaunak Saha
Enable SataPortsEnableDitoConfig for port 1. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons
The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/lippert/frontrunner-af: Drop commented-out Kconfig symbolAngel Pons
Drop it before it grows moss. Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork: Change SPI fast speed to 66mhzRob Barnes
Morphius cannot support 100Mhz fast SPI causing it to not boot. Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe. BUG=b:161233767 TEST=Boot morphius Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/oak: Add new DRAM modules for oakwuxy
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010 BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours. Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com> Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-14mb/hatch: Fix Puff baseboard missing mainboard symbolsEdward O'Callaghan
Fix a missing CONFIG_ prefix in Makefile. BUG=b:161154280 BRANCH=puff TEST=builds Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11 Spotted-by: Ryan Lin. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-30 18:22:23 +0000