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2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17ec/lenovo/h8/acpi: Add alternative Fn-F2 and Fn-F3 layoutNicola Corna
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and the lock hotkey (KEY_COFFEE) on scancode 0x02. On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2 and Fn-F3 are different from the default one so a new layout has to be defined. Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-17mb/google/slippy: Fix IRQ of the ambient light sensorNicolò Veronese
Change based on google/auron that is similar to peppy. This will be helpful for the next follow-up commit that will add ACPI for the ambient light sensor. Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3 Signed-off-by: Nicolò Veronese <nicveronese@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-17mb/google/drallion/variants/drallion: Update thermal configuration for DPTFJohn Su
Follow thermal table for fine tuning. 1. Update PSV values for sensors. 2. Change PL1 min value from 4W to 5W. 3. Change PL1 max value from 15W to 12W. 4. Change PL2 min value from 15W to 12W. BUG=b:148627484 TEST=Built and tested on drallion Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-02-17mb/google/drallion: Set cpu_pl2_4_cfg to baseline for DrallionJohn Su
Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg. BUG=b:148912093 BRANCH=None TEST=build coreboot and checked IA_TDC from TAT tool. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-17mb/google/octopus/variants/dood: add two new SKU IDsKenneth Chan
add SKU ID 3 and 4 for dood DVT 1: Dood WiFi + LTE (evt) 2: Dood WiFi (evt) 3: Dood WiFi + LTE + dual camera (dvt) 4: Dood WiFi + dual camera (dvt) BUG=b:148988979 TEST=build firmware and verify on the DUT of sku 3 and 4 check LTE module is enabled or not Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/drallion: Correct USB3 OC pin configurationEric Lai
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly. BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/puff: Enable SPD_READ_BY_WORD to short the boottimeJamie Chen
Puff uses the smbus to access the SPD of memory DIMMs. It will short the SPD reading time if enabling SPD_READ_BY_WORD. BUG=b:149360051 BRANCH=None TEST=build puff and boot up OS ran cbmem -t | grep FspMemoryInit Without this patch: 950:calling FspMemoryInit 643,199 (257,588) With this patch: 950:calling FspMemoryInit 477,714 (154,612) Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-02-17mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53Jitao Shi
Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The parameters are based on BOE NV101WUM-N53 preliminary product spec. BRANCH=kukui BUG=b:147378025 TEST=bootup pass Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/kukui: Add panel for KakaduCasper Chang
Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed BRANCH=kukui Signed-off-by: Casper Chang <casper_chang@bitand.corp-partner.google.com> Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822 Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/octopus: Add custom SAR values for BipshipTony Huang
Bipship is a sustaining project of Blooguard. SAR value follow Blooguard. BUG=b:149414960 BRANCH=octopus TEST=build and verify load correct SAR value by sku-id Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-17mb/google/dedede: Configure I2C portsKarthikeyan Ramasubramanian
Enable I2C ports that are used. Add GPIO configuration for the I2C ports. Enable config items that are required for I2C HID & Generic devices. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-17mb/google/dedede: Add console UART configurationKarthikeyan Ramasubramanian
Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/dedede: Enable AP <-> H1 CommunicationKarthikeyan Ramasubramanian
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I37972635454cd0d35608623e7be4110012ace658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17ec/purism/librem: Add ACPI temp reportingMatt DeVillier
Add EC ACPI reporting of current temp and platform critical temp. Adapted from ACPI dump of ODM AMI firmware. TEST: check reporting of current/critical temps via lm-sensors from ACPI on Librem 13v1 and 13v4 boards. Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17Revert "mb/google/hatch: Override CPU flex ratio"Tim Wawrzynczak
This reverts commit a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918. Reason for revert: The extra reset in the FSP after the flex ratio is changed causes recovery reasons to be lost. There are some vboot changes that recently landed that could help with this issue, but for now, we are working on a new AU image for Kohaku and this is causing our automated testing to fail. Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17mb/apple/macbookair4_2: Add CMOS supportEvgeny Zinoviev
Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-17vboot: push clear recovery mode switch until BS_WRITE_TABLESJoel Kitching
Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-15mb/intel/jasperlake_rvp: Enable only required PCIE root portsUsha P
Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports as per Jasper Lake. This patch updates the devicetree to enable WLAN and NVME for jasperlake_rvp and removes the other root port configurations which are not required. Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-14mainboard/supermicro: x11ssm-f: disable SUART3/4Michael Niewöhner
SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Further they break the console for an unknown reason. Thus disable them. Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-14mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4Michael Niewöhner
SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Thus drop the remaining settings. Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38817 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-13mainboard/supermicro/x11-lga1151: correct board idsMichael Niewöhner
X11SSM-F has a different board id (0896) than X11SSH-TF (089C). Use the right id for the right board. Change-Id: Ib0d5e66ce1a973f29a1da78f04f7ef677b260cd8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-13mb/pcengines/apu2: Remove unnecessary initializationPaul Menzel
The variable is never read before being assigned a value at the end of the function. Change-Id: I3b42dcd564480005b2c520316933940d87b6e418 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-02-13mb/pcengines/apu2: Use variable `len` holding same valuePaul Menzel
Change-Id: Ia5916f191a7b1a846231b7e36924a16f3a658961 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-02-11mb/google/volteer: use new Tiger Lake memory configNick Vaccaro
Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use Tiger Lake's new common code. BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, boot to kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB". Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8Wim Vervoorn
BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11mb/lenovo/x201/acpi_tables: Default to lid openPeter Lemenkov
It's really hard to power up this laptop with the lid closed so let's make it open by default, as done on many other laptops. Change-Id: I5bb2f716865c2bb569a4735f135842526043713c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-09mb/lenovo/t400: Configure panel-power sequencingNico Huber
If the panel-power sequencer is not configured, libgfxinit falls back to very conservative defaults (210ms before EDID is probed). This results in a boot penalty of >100ms (depending on how long it takes to probe other ports). Values are taken from the VBTs already checked in. Untested. Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for R500 variantNico Huber
The second digital display connector is unused, but strapped as if it were used. Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can ignore these. Based on schematics only, not tested. Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-02-09mb/lenovo/t400: Correct display port list for [TW]500 variantsNico Huber
T500 and W500 (Coronado-5) use both digital display connectors. Both with the DP AUX channel implemented, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for [RT]400 variantsNico Huber
The first digital display connector is unused, but strapped as if it were on later revisions. The DP AUX channel of the second connector is implemented, though, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Move `gma-mainboard.ads` to variantsNico Huber
Some board revisions have the straps for display port detection wrongly configured. So with a single list covering all variants' possible outputs, we make libgfxinit probe unimplemented ports which may stall the GMBUS controller and delay the boot for some hundred milliseconds. This just copies the list to the various variants with different display ports, so we can test the actual changes individually. Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/google/octopus/variants/lick: Increase TCC offset to 15Hash.Hung
Change tcc offset from 0 to 15 degree celsius for lick. BUG=b:147198431 BRANCH=octopus TEST=Build, and verify test result by thermal team. Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Change-Id: Ife6b02321145837e05c82f979998466b83317f86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add initial configuration for serial IO portsKarthikeyan Ramasubramanian
Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-09mb/google/dedede: Turn on ESPI device in devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add GPE configurationKarthikeyan Ramasubramanian
Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/dedede: Add Compute & PCH Global device IDsKarthikeyan Ramasubramanian
Add compute and PCH Global device IDs with the concerned devices turned off. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/volteer: add volteer mainboard initial supportNick Vaccaro
Created a new Google baseboard named volteer from scratch. BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/drallion: Add new SPD files for drallionIan Feng
Add new SPD files for drallion: 1. Hynix H5AN8G6NDJR-XNC 2. Samung K4AAG165WA-BCWE 3. Samung K4A8G165WC-BCWE BUG=b:148642500 TEST=Compile successfully and check SPD info in cbmem log. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/drallion: Tuning WWAN power sequenceEric Lai
Change GPP_C10 from pltrst to deep to meet the warmboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-09mb/google/dedede: Log mainboard events to elogKarthikeyan Ramasubramanian
BUG=b:148410914 TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/lenovo/t440p: Enable dGPU on Lenovo T440PChris Morgan
Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of the T430S. By default, it is set to be disabled however it can be enabled via the nvram option enable_dual_graphics. Removed hybrid graphics options too as they are not valid for the T440p. Tested on a T440P with Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine with Windows 10 1909 (machine check exception bluescreen). Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-09mb/google/octopus: Override VBT selection for BloogTony Huang
Since most of Bloog series SKUs need to disable DRRS support. If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support, return vbt_blooguard.bin for other SKUs to disable DRRS support. Bipship follow blooguard to disable DRRS support. BUG=b:148892903, b:147021309 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is bipship. Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-08Add configurable ramstage support for minimal PCI scanningRonald G. Minnich
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-02-07mainboard/hatch: Fix puff DP output on cold bootsEdward O'Callaghan
Wait for HPD DP unless HDMI is plugged. Some Type-C monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Similar to that of b:72387533 however our DP&HDMI are beind a MST. See commit d182b63347c744c on how this was done for mainboard/fizz. BUG=b:147992492 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2020-02-06mb/pcengines/apu2: use AGESA 1.0.0.4 with adjusted AGESA headerPiotr Kleinschmidt
PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA 1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which is compatible with AGESA 1.0.0.4 version. Cut out the changes introduced in CB:11225 exclusively for apu2 board. TEST=boot PC Engines apu2 and launch Debian Linux Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876 Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-06mb/google/hatch: Add noise mitigation setting for dratini/jinlonWisley Chen
Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8 and disable Fast PKG C State Ramp (IA, GT, SA). BRANCH=hatch BUG=b:143501884 TEST=build and verify that noise reduce. Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05mb/google/drallion: Fine tune touch screen power sequenceEric Lai
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing. BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05mb/google/hatch: Correct PCIe ports setting for mushuAmanda Huang
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci. Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-11 06:23:34 +0000