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2016-03-25google/intel mainboards: Add missing board_info.txt filesMartin Roth
The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14117 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-21soc/apollolake: Add skeleton ACPI entryLance Zhao
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-21nb/intel/sandybridge: increase MMCONF_BASE_ADDRESSPatrick Rudolph
Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. The sandybridge chipset code assumes 64 pci buses behind MMCONF. Therefore, only 64MiB of physical address space is required. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible to use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-03-21google/oak: Move external buck initialization to coreboothenryc.chen
Remove the code which is passing parameters to ARMTF and move external buck initilizaton from ARMTF to coreboot. BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I4f4b30acbee9b42a202b326f2fe4517cb4b9d83c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37bec54b4d8a3bce38878e292e4821da3959026a Original-Change-Id: Ib81709812a064f6daf13c9b4d6525f1858c81393 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332343 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mainboard/intel/galileo: Enable SPI controllersLee Leahy
Enable the SPI controllers on the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when the time is able to be displayed on a set of seven-segment displays controlled by a Maxim MAX6950 SPI display controller. Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18google/oak: Enable RAM_CODE_SUPPORTYidi Lin
BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16skylake mainboards: Configure gpio PADRSTCFG to PLTRSTNaresh G Solanki
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15pcengines/apu1: Enable USB overcurrent detection.Tobias Diedrich
The two external USB ports and the internal USB header have overcurrent protection chips with the low-active overcurrent signal connected to the chipset. The power-on default for this register disables the software detection of overcurrent conditions. After setting the register Linux correctly shows the overcurrent condition in the kernel log (tested by shorting the 5v and gnd lines on J14 / the internal USB header): [ 2015.229921] usb usb1-port3: over-current condition [ 2015.449925] usb usb1-port4: over-current condition Simlar for the external ports: [ 256.237916] usb usb1-port1: over-current condition [ 256.458084] usb usb1-port5: over-current condition Note that each signal is shared between two ports: usboc0#: External ports (port1/5) usboc1#: Internal ports (port3/4) Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/14084 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15lenovo: add config ONBOARD_VGA_IS_PRIMARYPatrick Rudolph
Fix for the T4xx and T5xx series. It does not apply to X2xx/X6x series as those have only one GPU, which is always connected to the display. The T6x series needs special care not handled with this patch. Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be deactivated in case a dedicated GPU is found and active, leaving the system without a working display. Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-03-15google/oak: add table for 4GB configurationPH Hsu
BRANCH=none BUG=chrome-os-partner:49229 BUG=chrome-os-partner:50806 TEST=power on to kernel on Oak Rev3 with 4GB dram Change-Id: I32fa881df12eb9b7f66086904aebde3dd1483fbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15google/oak: Remove EC_SUSPEND_L from APKoro Chen
This pin is not used anymore since Rev5. BRANCH=none BUG=chrome-os-partner:49375 TEST=make and boot on Rev4/5 Change-Id: I3c775eb2b5e05256523bfd8be814e516944a2f90 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a87e3babe28413bd879a2d95d4612a5b6b541419 Original-Change-Id: I87972ff8961309ecdad03639e1b6fac1da119cd7 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331810 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14087 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PMmgarima
Enable SDHCI runtime PM since the display flicker due to SCC Power Gatingis addressed by 0x82 microcode BRANCH=glados BUG=chrome-os-partner:44663 TEST=Check if display flicker is gone when SCC is power-gated Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3 Original-Signed-off-by: Medha Garima <medha.garima@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329651 Original-Commit-Ready: Jenny Tc <jenny.tc@intel.com> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331172 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12glados/chell: send an extra VR mailbox commandRizwan Qureshi
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12mediatek/mt8173: detect sdram size at runtimeYidi Lin
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect the DRAM size at runtime. BUG=chrome-os-partner:49427 BRANCH=none TEST=Boot to kernel Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223 Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327961 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331176 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: pll: raising the CPU core frequencyYidi Lin
Runs the LITTLE core at highest freqency to speed up the boot time. Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.) BRANCH=none BUG=chrome-os-partner:47422 TEST=flash the bootloader and measure the boottime by cbmem result Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161 Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/324685 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Configure USB OC pinsYidi Lin
BRANCH=none BUG=none TEST=none Change-Id: If7244d0050833c676de72106d1c8473dd8f290a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89356785e66eb6d5b52fdf09933d2d28d9f67a90 Original-Change-Id: I94dda9834da6553795e7f3f65ff267fdcb6b7d47 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321055 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13977 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config USB Hub for rev5Ben Lok
Reset pin of USB Hub is connected to GPIO118, it is low active. Config GPIO118 as GPO and output high. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I630cfd1c1019447736e7e5b286790fead4bdcfb6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b5cd98d0b3c5d2bab408ecebebc924d1f2b7df Original-Change-Id: I1ea0e1baac3da4d13301307f01bbe51e108298dd Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321054 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config audio for rev5Koro Chen
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ibdafa4ffe0baf5231654e67612b7ca59d835b602 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 63fedfec26ba1444934e348ce59609fa88e12de5 Original-Change-Id: Ifbbf8d2b3b6e163481843308c2e3edc4a55f90c6 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319988 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Remove obsolete Rev0 settingKoro Chen
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I65aa87e88cf812fdb490933de1a3b121866a2694 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f703f7e71ae6ffc0f1ac0e70486d087a28da5ba Original-Change-Id: I8d794464d45ea69f9a46f7ebc505f6ec2127f204 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319987 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13974 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Enable TP_SHIFT_EN for the revisons before 5 onlyYidi Lin
BRANCH=none BUG=none TEST=emerge coreboot Change-Id: Ic46490a56a6a8146b91a055b9ce5d5bb23bc7a49 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 082ce1848bf37bba369fd0dccc4cf3fc83a8a018 Original-Change-Id: I58f009d2fc03cf5a52b4dbd042a92973cde4d035 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320029 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13973 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: da9212 gpio configuration for rev5henryc.chen
BRANCH=none BUG=none TEST=none Change-Id: Ib44a9e8ca94727809e47831228f4742c25a53977 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: da9185c22264440da822aa252c0c5d2aef78b455 Original-Change-Id: I98c2ad757d0cd0e3234e49392091784b43a106e7 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320028 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13972 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config PANEL_LCD_POWER_EN for rev5Yidi Lin
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ic2019a1d61cbc5949c1f42346b279ef05f725dfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf13606f01438bc2ea27ecccc6359a7320dc34cc Original-Change-Id: I3fcc403cb7a3429b9673be0e727fc7d8c9d4f556 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320027 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Configure SPI_LEVEL_ENABLE pin for rev5Yidi Lin
Oak introduces a 1.8V to 3.3V level shifter for EC SPI bus after rev5. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I71868b003fc71dee0532033299afc155a9fbec9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030b478fedf046a7b818696779299c591415fcbd Original-Change-Id: Ibff9705832700867279cb1b39b752b8f5f27cf33 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320026 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13970 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Initialize i2c bus timing register for TPM and external buckjun.gao
BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: add event logCC Ma
BRANCH=none BUG=none TEST=boot to shell on Rev3 Change-Id: Ifca80705e392ce171ef33bf98ef787e3cd5ffd6b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56 Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303207 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Add soc ARM Trusted Firmware supportJimmy Huang
We define a mechanism to pass board specific parameters to BL31. The idea is BL31 doesn't need to have the board revision knowledge, it only needs to process the board specific parameters to initialize and control specific hardware. In this way, we can support different boards with same BL31 binary. BRANCH=none BUG=none TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got different board arguments in ARM TF Change-Id: I0df2c6d7d1ffac7d443511c3317c142efeb5701e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292678 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13101 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Initialize DRAMPeter Kao
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mt8173: add SPI NOR supportmtk05962
BRANCH=none BUG=none TEST=boot oak to kernel on rev1 Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18 Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292693 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10mainboard/intel/apollolake_rvp: Populate static devicetreeLance Zhao
Add configuration in accordance to "PCI Configuration Matrix". Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13926 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-10cpu/via/c7: Don't manually include udelay_io.cStefan Reinauer
Use UDELAY_IO selected by CPU_VIA_C7, so no manual inclusion (or secondary UDELAY implementation) is needed Change-Id: Ib086a1bfe8ffca5757bf553c5a62a45da7a410b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10mainboards/google/auron_paine: add new portGeorg Wicherski
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine code originally from commit bd61dfd in Google branch firmware-paine-6301.58.B . Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: https://review.coreboot.org/11907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09mainboard/intel/apollolake_rvp: Add memory training configLance Zhao
Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08nyan: Fix timestamps and CBFS SPI integrationJulius Werner
Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13832 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-08mainboard/skylake: Include WRDD method in WIFI ACPI deviceDuncan Laurie
Include the code to add the WRDD method to the existing WiFi Device in the mainboard ACPI code. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Compile for the other platforms that are modified. Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516 Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329296 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13840 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-08Kconfig: Remove unneeded UDELAY_IO redeclarationStefan Reinauer
UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does not need to be redefined in the AMD cpu or board Kconfigs. Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13780 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08roda/rk9: Remove #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Also re-organize some of the superio code in order to succesfully compile the rom. Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07mainboard/intel/galileo: Enable SD flash cardsLee Leahy
Turn on the SD controller to allow it to claim resources. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the SD flash card * The "drivers" command shows an SD host and SD media connection Change-Id: I883dc87270045786ddb931bea83fc36646a128e6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05amd/thatcher: Removed #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13887 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 Reviewed-on: https://review.coreboot.org/12087 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29google/chell: Update DPTF configurationDuncan Laurie
Update the DPTF configuration for the chell mainboard: 1) Enable DPTF charger control, set max current to 1975mA according to the battery specification. 2) Enable charger effect on charger temp sensor in TRT 3) Set PL2 to 15W which is the same value configured in the CPU. BUG=chrome-os-partner:49859,chrome-os-partner:50306 BRANCH=glados TEST=build and boot on chell Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329187 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13842 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29google/chell: Update GPIOs for DVT2Duncan Laurie
Add new GPIOs for touchscreen enable and reset pins and define the one missing unconnected pin for GPP_E10. BUG=chrome-os-partner:50518 BRANCH=glados TEST=build and boot on chell DVT1 Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329297 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13841 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29mainboard/google/chell: provide configuration for all padsAaron Durbin
Instead of relying on power-on-reset values provide configuration for all pads. PAD_CFG_NC() was used for all pads which had no nets routed on the board. PAD_CFG_GPO(0) was used for pads which had nets routed on the board in order to terminate them. BUG=chrome-os-partner:50301 BRANCH=glados TEST=Built and booted chell. Suspended and resumed on EVT. Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9 Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/327835 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13831 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 05:49:35 +0000