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2020-06-03mb/google/zork: Add HID for max98357aRaul E Rangel
The default HID was removed by a1c82c5ebee. We need to explicitly specify it. BUG=b:154756391 TEST=No longer see ERROR: _HID required message in console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-03mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetreeArthur Heymans
These devices never show on the PCI domain. Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/gigabyte/ga-g41m-es2l: Add PEG to devicetreeArthur Heymans
Change-Id: Icebf0eea4e1fee6d15ba3f1a080cbc40b42fd733 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03mb/aopen/dxplplusu: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Board does not support ACPI S4 or C-states or P-states. Change-Id: If83efb72e076d404468259e312a5afac625f04af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03Makefile: Drop HAVE_SMI_HANDLER test for smm-classKyösti Mälkki
Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubsKyösti Mälkki
Board does not have ChromeEC. Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC testsKyösti Mälkki
Boards have unconditional select EC_GOOGLE_CHROMEEC. Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03mb/bap/ode_e21XX: Drop old commented KconfigsKyösti Mälkki
Change-Id: I56225c0a533e5f9e8294b7866a41c9a6c24a7f67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03mb/google/zork: Delete sb_fch.aslRaul E Rangel
This file is not used. BUG=b:154756391 TEST=Build trembyle and check that peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/hatch: Enable the CSE Lite SKU for Puff variantsV Sowmya
This patch enables enables the CSE Lite SKU for all the puff variant boards. BUG=b:143229683 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/hatch: Modify the puff fmd files to support CSE Lite SKUV Sowmya
This patch modified the puff fmd files to support CSE Lite SKU. * Reduce the SI_ALL size to 3MiB since ME binary size is less than 2.5MiB. * Increase the FW_MAIN_A/B size to accommodate the ME_RW update binary with CSE Lite SKU. BUG=b:154561163 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03mb/google/volteer/halvor: initialize gpio setting and update overridetree.cbFrank Wu
Based on schematic and gpio table of halvor, generate gpio setting and overridetree.cb for halvor. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the image-halvor.bin is generated successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/deltaur: Change H1 I2C speed to FASTEric Lai
H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM. Therefore change I2C speed back to FAST. BUG=b:154885320 TEST=Check H1 I2C speed is 375kHz by scope. And no error message in cbmem and kernel log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If58721039d90514a17f024e6b432f3a5226440e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-06-02mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllersJohn Zhao
This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting. BUG=:b:146624360 TEST=Built and booted on TGL RVP. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02mb/google/volteer/ripto: Add audio devices to the treeDuncan Laurie
The ripto board is still being used for testing so make sure it supports the same audio config as volteer. BUG=b:147462631 TEST=build ripto variant Change-Id: Iabeb73307418dc16b12fa60ad26923cd9f6e1f3a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-06-02mb/google/volteer: Add firmware configuration probing for audioDuncan Laurie
For all of the audio devices in devicetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others BUG=b:147462631 TEST=test different device present in ACPI based on fw_config value: > AUDIO=NONE ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682I_I2S ectool cbi set 6 0x00000200 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000300 4 2 Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41216 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Add firmware configuration tableDuncan Laurie
Add the current firmware configuration table for the volteer mainboard and define some actions based on probe results for audio: - When I2S options are selected disable the SoundWire GPIOs. - When SoundWire is enabled disable the I2S GPIOs. - When no audio is enabled disable all the GPIOs. BUG=b:147462631 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi. Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Reorganize audio codecsDuncan Laurie
- Move all audio devices from baseboard to the volteer variant. - Add max98373 devices and enable the driver - Disable everything in FSP and let coreboot configure GPIOs. BUG=b:147462631 TEST=this change makes all audio devices show up in ACPI, so this was tested by ensuring that all audio devices are present in ACPI. Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPMKyösti Mälkki
Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02mb/purism/librem*: drop EC chip deviceMatt DeVillier
CB:35086 exposed that the devicetree listed an EC chip for which there is no actual driver; the EC is entirely ACPI code (.asl) included by the board's ec.asl. Remove the unnecessary EC chip driver from both boards, as well as the unnecessary Kconfig selection for librem_bdw. Test: build/boot Librem 13v1, 13v4, verify battery info etc still correct. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02mb/lenovo/x230: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad X230 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291 Signed-off-by: Stefan Ott <stefan@ott.net> Tested-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40669 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vbe.h>'Elyes HAOUAS
Change-Id: I7c0be437e8cb49934913563c6d21056034a50095 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cbfs.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove duplicated includesElyes HAOUAS
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused 'include <arch/smp/mpspec.h>'Elyes HAOUAS
Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/asus/p2b: Add p3b-f IRQ routing to DSDTKeith Hui
Change-Id: Ie4d24eee1cffd65707887dd621e3de873d20cf01 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZEKyösti Mälkki
Remove the use of C_ENV_BOOTBLOCK_SIZE. Verify the bootblock by reading the CBFS file instead of directly accessing the datablock. BUG=None BRANCH=None TEST=tested on facebook fbg1701 Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41694 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02drivers/vpd: rename VPD_ANY to VPD_RO_THEN_RWJonathan Zhang
Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search preference. Update all existing code references for VPD_ANY. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Enable TCSS DMA0 for VolteerJohn Zhao
This explicitly enables TCSS DMA0 controller and disables TBT PCIe2 and PCIE3 since they are unused on volteer. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/dedede: Enable GBB configs for dededeUsha P
This patch enables the necessary GBB configs for dedede BUG=none BRANCH=none TEST=GBB Flag value was 0x39 before enabling the required flags and now it is updated to 0x40b9. Verfied from CPU log. Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-06-02mb/google/dedede: Add SD card supportAamir Bohra
1. Configure SD card GPIOs. 2. Set SD card power polarity and card detect configs. SD card CMD. DATA and CLK GPIOs are set for native pad termination as per recommendation in EDS vol1 section 10.4.10 BUG=b:150872580 TEST=Verify SD card enumeration and read/write transactions. Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/google/dedede: Enable coreboot lock down configAamir Bohra
TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-01src: Fix up #-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01mb/asrock/b85m_pro4/cmos.layout: Remove copyright noticesAngel Pons
Change-Id: I2aaabec17073c0a2ccd40de068223a9215186db3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01mb/asrock/e350m1: Do not redefine AGESA_VERSION_STRINGAngel Pons
This is the only AGESA f14 board which has a different version string. As it is most likely a copy-paste error, drop the redefinition of this macro from buildOpts.c and use the value defined in AGESA f14 headers. Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-01AGESA f14/f15tn/f16kb: Clean up buildOpts.c filesAngel Pons
Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-06-01mb/google/hatch: Add Noibat variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/dedede: Enable Heci1 deviceAamir Bohra
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-29mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16Marco Chen
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/hatch: Select the fmd files for puff baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files to align with basebaord name and layout size. BUG=b:154561163 TEST=Built puff and verified that it selects the right fmd file. Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select the fmd files for hatch baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to add the baseboard name and layout size tags. BUG=b:154561163 TEST=Built hatch variants and verified that they select the right fmd files. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select BOARD_ROMSIZE_KB_16384 by defaultFurquan Shaikh
All hatch and puff variants use 16MiB SPI flash except the legacy ones which used 32MiB flash. Kconfig.name is updated to select BOARD_ROMSIZE_KB_32768 only for the legacy variants and BOARD_GOOGLE_HATCH_COMMON selects BOARD_ROMSIZE_KB_16384 by default if BOARD_ROMSIZE_KB_32768 is not selected. TEST=Verified using abuild --timeless that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I708506182966936ea38562db8b0325470e34c908 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41662 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29AGESA boards: Fix typo in *OVERRIDES* in commentPaul Menzel
Run the command below to fix all occurrences. git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g' Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-05-29Puff: Disable EFS1 for variantsDaisuke Nojiri
VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2 and its variants should follow. BUG=b:157372086 BRANCH=none TEST=emerge-puff coreboot Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-28mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for VolteerTim Wawrzynczak
Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28mb/google/dragonegg: remove abandoned projectAaron Durbin
Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/zork/berknip: Replace full GPL header with SPDX linePatrick Georgi
Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-16 00:22:08 +0000