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2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-15mb/google/hatch: Enable TBMC deviceDtrain Hsu
This change enables tablet mode ACPI device for all hatch boards. BUG=b:125355874 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I4d3818497172828d750b34fe91cbb6cc65e69fc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'Elyes HAOUAS
Change-Id: I380ffe1348731b8c84855047e057365bec94a08c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-14mb/google/kahlee/aleena: Add EC_ENABLE_TBMC_DEVICEEdward Hill
Enable ACPI TBMC notification on tablet mode change to support convertible Aleena devices. BUG=b:124132058 BRANCH=grunt TEST=evtest shows tablet mode events Change-Id: Iaf8ef031d4660f0791b5f664880437e6dfa58dc8 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-14mb/google/arcada: Update USB2 port6 AFE settingLijian Zhao
Accoriding to 574354, we need to tune each port to pass eye diagram other than just use recommanded setting as they are base guidence only. Bug=b:124407280 TEST=Build and boot up on arcada board. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I587695809b368edd33852c4241de097ca31e9d66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31632 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Define GPP_C13 as EC_SYNC_IRQPhilip Chen
BUG=b:125933998 CQ-DEPEND=CL:1510513 BRANCH=None TEST=manually verify on hatch, chromeos-ec interrupt count increases Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I1dd38ca5aed1e0ddecb4738910cbfa92de33d315 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31814 Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14src/mainboard/pcengines/apu2: Bring back copyrightsMichał Żygowski
The copyright notices of Eltan B.V. have been removed by mistake before sending the patch with board support. Revert back to be consent with the license. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic5948ab60a661ef78e4e5c8571535a096fc88ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-03-14gigabyte/ga-h61m-s2pv: fix PS/2 ACPIAngel Pons
Change-Id: Ia806d8470aa36e04f1b0b714a80d4e7b1eb80100 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-14mb/google/hatch: fix RCompResistor[0] valueShelley Chen
From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information User Guide, RCompResistor[0] should be 121. BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Update DRAM IDsShelley Chen
Update Hatch DRAM IDs to use the new DRAM ID assignment for general spds: 0 = 4G 2400 1 = 4G 2666 2 = 8G 2400 3 = 8G 2666 4 = 16G 2400 5 = 16G 2666 BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-14mb/google/hatch: Use MEM_CH_SEL to indicate single_channel skuShelley Chen
MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field (from GPP_F2), which will in turn initialize MemorySpdPtr pointers in cannonlake soc code. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-14mb/google/octopus: Create Bloog variantTony Huang
This commit create bloog variant for Octopus. Initial settings are copy from meep. Remove I2C tuning, WACOM digitizer and WEIDA touchscreen. Override GPIO configuration for unused LTE and Pen. BUG=b:127736039 BRANCH=octopus TEST=None Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-14mb/google/hatch: Query the EC for board versionIvy Jian
The board version is part of EC's EEPROM, select Kconfig items to enable requesting the EC for board version. BUG=b:128385395 TEST=Verified the mainboard version is from EC's EEPROM. Change-Id: I4bc1cac43c6cf73522f3a4bee89cc000a430d996 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31858 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/arcada: add Kconfig option to enable WLAN SARCasper Chang
Enable WLAN SAR power table. BUG=b:123552641 TEST=Verified WLAN SAR power table forllows VPD setting Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I882b1c7ed0b1142a84eb338142e1c984df45eeba Reviewed-on: https://review.coreboot.org/c/coreboot/+/31859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-14mb/lenovo/x1_carbon_gen1/cmos: Port USB Always OnPatrick Rudolph
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On" to the Thinkpad x1_carbon_gen1 board as well, as it seems to work fine on all generations. See also commit 7ffb329f with Change-Id I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 ("mb/lenovo/*/cmos: Port USB Always On"). Note that we don't need to call h8_usb_always_on() directly since commit 4f4322dd with Change-Id If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a ("lenovo/h8,thinkpads: Re-do USB Always On"). Change-Id: Ib9070b659b0c9ad5dde4200ec2845c6fa2b78b25 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2019-03-14mb/lenovo/x1_carbon_gen1/acpi: call MUTE(1) and USBP(0) on _PTSNicola Corna
Like with any other Thinkpad, call MUTE(1) and USBP(0) on _PTS on the Lenovo Thinkpad X1 Carbon 1st generation. Without MUTE(1) the speakers sometimes glitch before going into S3 (if not muted), while without USBP(0) the USB ports are always powered in S3, regardless of the USB Always-On mode selected. Change-Id: I86f3c5a72e2589c5570303bf68f39df3ef874cb8 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-13mb/google/hatch: Provide DRAM part number from EEPROMFurquan Shaikh
This change reads DRAM part number from EEPROM if available and returns it using the SoC callback (mainboard_get_dram_part_number). BUG=b:127609572 TEST=Verify that DRAM part number from EEPROM is added to DMI table 17 (dmidecode -t 17). Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-13src: Drop unused 'include <arch/ioapic.h>'Elyes HAOUAS
Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN()Elyes HAOUAS
Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30787 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS
Change-Id: I315721d6261e558c3f7145c80714262052ce0e49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31783 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS
Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-12mb/facebook/watson: Enable TPM 1.2 supportzaolin
Enable TPM 1.2 via Kconfig options and devicetree. Change-Id: I394195b3117c8583b6b506d6ad4f5170d2f45f9f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-03-11mb/google/hatch: Add Hatch_whl boardShelley Chen
Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL version of hatch so that we can rebuild the bios images for Hatch with WHL SoC. BUG=b:127310803 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_WHL is built as well. Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-11mb/google/hatch: Enable audio supportSathya Prakash M R
Following changes are done to enable audio support on hatch 1. Enable I2C4 device at 400Khz at 1.8V 2. Configure GPIO for HP INT and SPKR_PA_EN 3. Add ACPI entry for RT5682 and MAX98357A 4. Enable I2S0 and I2S1 lines 5. Enable generic max98357a driver in Kconfig BUG=b:123738217 BRANCH=none TEST=Check SSDT table for RT5682 & MAX98357a entry. Verify audio using Sound Open firmware (SOF) Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08commonlib/loglevel.h: Drop unnecessary includeElyes HAOUAS
This 'include' is only needed in console/console.h file. Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-08src/mb: Shorten 'include <arch/x86/include/arch/acpigen.h>'Elyes HAOUAS
'include <arch/acpigen.h>' is good enough. Change-Id: Idc96376571715f5dd2c386f187b5c6d1613accee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31779 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08mb/google/hatch: Create hatch_whl variantShelley Chen
In preparation for the transition of hatch from WHL to CML, we are creating a checkpoint called hatch_whl that we can use for creating firmware compatible with the WHL hatch variant. BUG=b:127310803 BRANCH=NONE TEST=NONE Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08mb/google/hatch: Initialize all gpiosShelley Chen
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.hElyes HAOUAS
Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-07mainboard/google/kahlee: Add additional Micron MT40A512M16TB-062E:J SPD for ↵Kevin Chiu
variants BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06mb/google/poppy/variants/nami: Use Pantheon VBTJohn Su
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06mb/google/sarien: add ish firmware_variant field to _DSDJett Rink
We want to publish "arcada_ish.bin" as the fw name for Integrated Sensor Hub (ISH) so the kernel shim loader code can use it to construct the correct path in /lib/firmware/intel for the firmware load process. BUG=b:122722008 TEST=Verify that shim loader CLs use new value when constructing firmware path Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-06ec/lenovo/h8: Implement ACPI methods to set battery thresholdsAlexey Kharlamov
There are two known reverse-engineered ways to manage battery thresholds. This patch implements them and adds a way to enable them for different mainboards. Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11. Works fine with new Linux userspace API for controlling battery thresholds, available since 4.17. (/sys/class/power_supply/BAT0/charge_(start|stop)_threshold). The new API is supported by TLP (you might need to set NATACPI_ENABLE=1 in /etc/tlp.conf). tpacpi-bat works fine too. Signed-off-by: Alexey Kharlamov <der@2-47.ru> Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"Elyes HAOUAS
Change-Id: I58ecd95a8427eba87611dd8ea4616aedbb1d01c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05mainboard: Enable PRESERVE flag in all vboot/chromeos FMD filesHung-Te Lin
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-05mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstageArthur Heymans
Qemu does not have a real CAR but postcar stage is still useful for testing the stage. The postcar stage is also mandatory for x86_64 to setup pagetables for x86_64 ramstage. Do not set up MTRRs, as qemu ignores them anyways. Tested on qemu-i440fx and qemu-q35. Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-05arch/io.h: Drop includes in fam10 romstagesKyösti Mälkki
These files suffer from .c includes. Change-Id: Id836595290922fcbd108a5ed576fc640b2530711 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31696 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05mb/google/sarien/variants/arcada: Add GPIO H15 to enable BTCasper Chang
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#). BUG=b:123342945 TEST=Verified BT function on Arcada DVT1 system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-05mb/google/octopus: Add 6GB dual-channel memory configurationSeunghwan Kim
Add 6GB dual-channel memory configuration for future use. BUG=b:124634885 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31460 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04Fix indirect include for endianessKyösti Mälkki
The function (preprocessor macro) we need is defined in <endian.h> not <swab.h>. Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 04:29:15 +0000