Age | Commit message (Collapse) | Author |
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The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.
Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add NHLT and dt support for meowth with max98373 amp.
BUG=b:71724897
TEST='emerge-meowth coreboot' compiles correctly
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".
This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.
Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.
Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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... and fix them in the process.
The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.
Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.
With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.
The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.
BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)
Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.
BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.
Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does no support eMMC so no need to configure it.
Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does not have memory down, only 2 DDR4 Slots.
Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.
BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Show mainboard version in the console log so that one can easily see it.
Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:69011806, b:72179988
BRANCH=master
TEST=Verify touchscreen on meowth works with this change.
Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/23551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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TEST=Run powerd_dbus_suspend and resume with button press
BUG=b:69614064
Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22732
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fine tune 14" BigDaddy USB#2 2.0 strength:
PERPORTPETXISET: 7
PERPORTTXISET: 1
IUSBTXEMPHASISEN: 3
PERPORTTXPEHALF: 0
this value could have USB#2 2.0 EA/function pass.
BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23649
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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acpi_header_t
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.
Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.
BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This change makes Nami platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:70646770
TEST=Verify kernel reads new strings.
Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S
converter.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove manually written asl entries for grunt's DA7219 and MAX98357A
audio codecs, and replace them with equivalent devicetree entries.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Add support for KBL RVP8 board
* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.
TEST= Build and boot RVP8.
Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch revises AC/DC loadlines from VRTT reports.
+----------------+-------+-------+-------+-------+
| Domain/Setting | SA | IA | GTUS | GTS |
+----------------+-------+-------+-------+-------+
| AcLoadline | 11 | 2.4 | 3.1 | 3.1 |
| DcLoadline | 10 | 2.46 | 3.1 | 3.1 |
+----------------+-------+-------+-------+-------+
BUG=b:72351128 b:72129954
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings
are passed to FSP.
Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
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* micbias_lvl -> micbias-lvl
* mic_amp_in_sel -> mic-amp-in-sel
BUG=b:71875600
TEST=Checked in kernel the values are set
Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/23603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build gardenia.
Change-Id: I24a71490777b101b069175460f3715ec3ff78240
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).
Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.
BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.
This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.
Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build kahlee.
Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix coding style
Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23523
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB
for size for video RAM.
Order the entries like in `cmos.layout`.
Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enable HotPlug for the PCIe root port that the WiFi device
is on so the OS can re-train the link without needing a reboot
if it goes down unexpectedly at runtime.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in
linux that it is identified as a HotPlug capable root port.
Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize non-early i2c buses in ramstage.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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