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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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* Change power sequence to make it closer to ov8856 sensor
data sheet version 2
* Handle different PWREN GPIO pins for up3 and up4
* Add link frequencies definitions to sensor side
* Clean up format
BUG=None
BRANCH=None
TEST=Build and boot TGLRVP U or Y. Start camera app and able to
capture images.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39529
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Method RAOW is assuming that the first argument is a Field object
and writing to it expecting the register to get updated. However,
the callers are passing in the value of the Field object instead.
This eventually is resulting the IMGCLK not getting enable/disabled on the
platform.
Fix this by sending the exact address of the register to be updated.
Also MCCT was setting the clock frequency in both case i.e, Clock Enable
and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing
like below
MCON:
Set frequency
Enable clock
MCOF:
Disable clock
Also, make use of MCON and MCOF methods for camera clock control in tglrvp.
This is to avoid the buildbot marking the patch unstable.
BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Foob360 would prefer to use different SAR values. Since Foob360
sku id is 9.
BUG=b:149362272
BRANCH=octopus
TEST=build
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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These platforms use the standard fixed function power button
and do not need a second power button device declared or the
kernel will end up with two devices reporting the same event.
Same change was applied to all google mainboards in
CB:27272 which contains more detail.
Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for waddledee variant board.
BUG=b:151576904
TEST=Build the mainboard and variant board.
Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3,
then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin
check "dmesg |grep ish", it shows:
ish-loader: ISH firmware intel/tglrvp_ish.bin loaded
cros_ec_ishtp: Chrome EC device registered
Those means shim loader in coreboot has loaded ISH firmware, and
firmware is running successfully.
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The X210 EC reports battery values in broken mAh. These have to be
adjusted by 10000 * DGVO, as documented in
https://github.com/torvalds/linux/blob/master/drivers/acpi/battery.c.
Taken from https://github.com/harrykipper/coreboot, commits
2f68f138adb25605e5715896636cf33f6de5bd95
c1c72cc43708a6647f263a767c39cf3072908e20
Change-Id: Ie097272443b18b16c3937034f874d3b5a6bdd62a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39142
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Add USB ports for SD card reader, fingerprint reader,
and internal port.
- Enable PcieRpClkReqSupport on NVMe root port,
correct values for ClkReq/ClkSrc.
- Improve comment for M.2-2230 USB port (BT)
Parts derived from x210_test branch of HarryKipper's repo:
https://github.com/harrykipper/coreboot
Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Derived from x210_test branch of HarryKipper's repo:
https://github.com/harrykipper/coreboot
Test: build/boot x210, test eDP, MiniDP, VGA outputs
Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:
* EC firmware is contained within the system SPI flash, and so a blob of
EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different
All hardware appears to work as expected, although the SD reader is
untested.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This is new Elan touch screen IC, which includes touch panel and USI pen.
BUG=b:151514167
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Consistently use the official uppercase spelling.
Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Palkia as a variant of Hatch.
BUG=b:150254194
BRANCH=none
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable GEO SAR function.
BUG=b:150347463
BRANCH=drallion
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.
BUG=b:151305120
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early ec sync needs to be disabled for EFS2 to function.
BUG=b:151115320
BRANCH=none
TEST=none
Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.
TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.
Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create new variant and build for nightfury.
BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add LPDDR3 4GB 2133MHz SPD file.
BUG=b:149226871
TEST=Build and check cbfs has the spd.bin
Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.
BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device
Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4
BUG=none
BRANCH=none
TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
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Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: I1bce09ba5041a6636f900de611846467653f35a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is required to transmit button information from EC to kernel.
BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff
Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.
Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality
Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables display for use by payload.
TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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