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This does not exist anywhere in the entire coreboot tree. Drop it.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Set the default CBFS size to cover the whole BIOS region.
Change-Id: If719a9cd2897d933df53bd423e71503b832411fe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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1. Configure GPIOs as per schematics
2. Add 1 Ports and 1 Endpoints
3. Add support for OTVI5675
WFC is on I2C5 with VCM support and using 2 data-lanes
BUG=None
BRANCH=None
TEST=Build and Boot jslrvp board and able to capture image
using world facing camera.
Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Currently coreboot is using the ec hardware id IBM0068 for all
thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268.
On Windows, the Lenovo Vantage app can't get battery details when using
IBM0068. This patch config this id by motherboard. The hardware IDs for
the following models can be found by searching for disassembled
dsdt.asl on vendor BIOS:
(But this info is not easy to find online. So I only changed some of
the thinkpads.)
T420:
https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl
LEN0068
T430:
https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl
LEN0068
T520: Confirmed by Patrick Rudolph
LEN0068
W520: Confirmed by Patrick Rudolph
LEN0068
T530: Confirmed by Prasun Gera
LEN0068
W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731
LEN0068
X230/X230T:
https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl
LEN0068
T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl
LEN0068
Signed-off-by: Da Lao <dalao@tutanota.com>
Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Other files in the tree use such license. I first added this file.
Change-Id: I338654ec022bd6f2fa4a4381a8f27d024605e79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The X230, like its larger cousins, has a docking connector. However,
it lacks the "docking_supported" flag in devicetree, so add it.
Change-Id: I188045e4cf9bbb0f2d434b353b84223470c951b9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41510
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this patch, the ThinkLight on the ThinkPad T400 can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T400 to test this.
Change-Id: I377854d6f54c5459e44626a7d7b61c513268183e
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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With this patch, the ThinkLight on the ThinkPad T430S can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T430S to test this.
Change-Id: Ifa74f5373a6305d1237e7de6da35028e68f1e99c
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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With this patch, the ThinkLight on the ThinkPad T420S can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T420S to test this.
Change-Id: I245acf81b34abccf7bcb04126275ab8b154135d5
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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With this patch, the ThinkLight on the ThinkPad T520 can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T520 to test this.
Change-Id: Iffc5dd2f23ee4896da633c18cbbf22c9e448edf1
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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With this patch, the ThinkLight on the ThinkPad T530 can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T530 to test this.
Change-Id: I94d239b65e6e8546a27f751d569681a4e68a4109
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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With this patch, the ThinkLight on the ThinkPad T430 can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T430 to test this.
Change-Id: I1fb1a9d3a84ce12ab9e3f22a699afbfd7cd1688f
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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On PC Engines apu1 there were issues with cold reset. Platform hangs
in boot path after performing reset using CF9h.
CB:10549 (amd/sb800: Make UsbRxMode per-board customizable)
mentions a similar issue, and added a configuration macro for it.
That error is also described in AMD SB800 Family Product Errata,
section 15 USB Resets Asynchronously With Port CF9h Hard Reset.
This workaround simply non-execute USB configuration during boot
and hence no reset via CF9h is done.
TEST=perform multiple cold resets and see if platform boots
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this patch, the ThinkLight on the ThinkPad X220 can be controlled
through the OS. This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own an X220 to test this.
Change-Id: Icead793694475e2f63353690203790ab7ce7c597
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40668
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this patch, the ThinkLight on the ThinkPad T420 can be controlled
through the OS. The same change was done for the ThinkPad X200 in
b45912f4: mb/lenovo/x200: Add support for ThinkLight
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Unfortunately I do not own a T420 to test this.
Change-Id: I4f9a9937a45995b72a9712919316e95bb8f82f45
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable drivers for SoundWire codecs and define the topology in
the devicetree for the volteer variant with the SoundWire daughter
board connected.
+------------------+ +-------------------+
| | | Headphone Codec |
| Intel Tigerlake | +--->| Realtek ALC5682 |
| SoundWire | | | ID 1 |
| Controller | | +-------------------+
| | |
| Link 0 +----+ +-------------------+
| | | Left Speaker Amp |
| Link 1 +----+--->| Maxim MAX98373 |
| | | | ID 3 |
| Link 2 | | +-------------------+
| | |
| Link 3 | | +-------------------+
| | | | Right Speaker Amp |
+------------------+ +--->| Maxim MAX98373 |
| ID 7 |
+-------------------+
This was tested by booting the firmware and dumping the SSDT table
to ensure that all SoundWire ACPI devices are created as expected with
the properties that are defined in coreboot under \_SB.PCI0:
HDAS - Intel Tigerlake HDA PCI device
HDAS.SNDW - Intel Tigerlake SoundWire Controller
HDAS.SNDW.SW01 - Realtek ALC5682 - Headphone Codec
HDAS.SNDW.SW13 - Maxim MAX98373 - Left Speaker Amp
HDAS.SNDW.SW17 - Maxim MAX98373 - Right Speaker Amp
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I7782059807416369e0e1ba0d4d7c79dcab0fcbc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40894
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of only using the baseboard devicetree add a placeholder
overridetree for volteer and refer to it in Kconfig.
This will allow us to add the volteer specific devices here instead
of at the baseboard level.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I7788a5473fc2275a9791fb27e0e4018a0efcd0f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40893
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM
part should be set to 0xF.
BUG=b:157178553, b:156555863
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a
SKU4 volteer to the kernel and run "memtester 6G 100" and verify it
completes successfully without error and does not crash.
Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD
contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f).
After fixing that error, I noticed that two generic SPDs could
be collapsed into one, so I removed one of the duplicate generic
SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex),
and changed Makefile to collapse volteer's DRAM ID 2 into ID 0.
BUG=b:156126658, b:156058720
TEST=Flash and boot a ripto to kernel. Also verified that ripto
can boot successfully to the kernel at 4267 MT/sec with FSP built
in debug mode with RMT enabled.
Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Other variants would be added later.
Change-Id: Ic6af14f0aa7a6f7378048f3c38d5713c18950366
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41509
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 6b95507ec5b087658178a325bdc68570bc48bb20, in order
to recommit and review it again.
Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I'm not quite sure what happened when we first added the code for
Trogdor strappings but something clearly seems to be wrong. First of
all, on newer schematics the RAM_ID_1 pin is actually pin 19, not pin
91. It only used to be 91 on rev0. Whether that was an intentional
change or someone just swapped the digits on accident at some point,
we're not quite sure anymore, but it seems to be 19 going forward so
that is what we should be programming. (ram_code wasn't used for
anything on Trogdor rev0 so we don't care about adding
backwards-compatibility for that.)
The sku_id pins are also somewhat out of whack: first of all, a new
SKU_ID_2 pin was added for rev1 that wasn't there on rev0. Second,
SKU_ID_0 is not GPIO_114. In fact, it has never been GPIO_114. I have no
idea how that number got there. Anyway, fix it. (Like with the ram_code,
SKU IDs were also not used for rev0 so we won't make this
backwards-compatible.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia14ec74ec2f16ce2661f89d0d597a5477297ab69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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Some Librem 13v4's don't have the presence straps connected,
leading libgfxinit to fail to init the internal display.
Select GFX_GMA_IGNORE_PRESENCE_STRAPS since all SKL/KBL Librems
have an internal display so there's no adverse effect.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ib9d281b7d495c4f9a5c6fc5fdb8042b0fcbda745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41417
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The devicetree declares the chrontel interrupt as GpioInt so the GPIO
needs to be configured as such instead of routing directly to APIC.
Also update the compatible string to conform to kernel standards.
BUG=b:146576073
TEST=install ch7322 driver; send commands using cec-ctl and verify
that the interrupt handler is called.
Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Enable DPTF functionality for volteer platform
BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system
Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.
BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
flags f0000200 index 0
PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
flags c0000100 index 1")
Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")
Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")
Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Link frequency and a format was not correct for volteer proto 2
ov2740 user-facing camera.
The link frequency is calculated in the following way.
(max frame width * max frame height * max fps * data format in bps
/ number of lanes / data rate) + max 35% of overhead
For ov2740, (1920 * 1080 * 60 * 10 / 2 / 2) = 311Mhz.
360Mhz after adding 18% of overhead.
BUG=b:148428976
BRANCH=none
TEST=Build and boot volteer proto 2 board. Start a camera app
and check user-facing camera functionalities.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I3b51826e123dec394c1b4eb9a1c5b64b8b11459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41157
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Volteer port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping. This
requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0)
and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can
control the orientation
BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped
Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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This enables EC software sync in romstage.
BUG=b:148259137
TEST=verified EC is updated in romstage using coreboot serial console
logs.
Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41078
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Deltaur uses CNVi WLAN module, this setting is not required.
BUG=none
TEST=WiFi is functional in OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add tcss.asl to support TCSS power management.
For the detail please refer cb:39785.
BUG=none
TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3
/sys/bus/pci/devices/bus:device:func/power suspend and
active time can increase.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add low power idle table to notify EC system is entering s0ix.
BUG=none
TEST=Power button and keyboard backlight are off when suspending.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Originally variants make use of a 32MB chip whereas now they
use a 16MB SPI flash. Allow for the coordination of dealing
with the transition between phases.
V.2: Leave Puff alone at the moment due to the complexity of
coordination.
BUG=b:153682192
BRANCH=none
TEST=none
Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unused includes found using following commande:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<'
Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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X230s and T431s have keyboard similar to the one found on t440p, so
H8_HAS_PRIMARY_FN_KEYS and related cmos options may apply to them.
Tested on both X230s and T431s.
Change-Id: I234820b92093acdd64ff60cae39015547b6e981e
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41403
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iad5540e791075270453a136a058823c28647f93a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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Change-Id: I7c6f47f03f1c83658f4364f81f6436d7b2f4f377
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.
Change-Id: I78f1e250570f1b395c61115d4a872b24b3d58f69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.
Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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The change applies the DPTF parameters received from thermal team.
1. Set PL1 Max to 25W
2. Set PL2 Max to 44W
3. Update Temp sensor parameters
BUG=b:152011093
BRANCH=none
TEST=build and verified by thermal team
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I225897832b02f9de6221053b68fbdba30f8b199a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41165
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Deltaur does not use DSP so remove the DSP setting.
BUG=b:155360937
TEST=Recording and playing are working fine in OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I01c076806448fc73980ec02e7558ccf082723d92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add audio verb table provided by vendor.
BUG=b:156447983
TEST=Have beep sound when run "devbeep" in CLI.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I807d84de1677459ea027e645488f485b0ac7b2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41401
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Deltaur uses HDA codec so we need to set iDisplay Audio Codec
disconnection and enable HdaAudioLink, otherwise the HDA codec won't
respond to commands to execute HDA verbs.
BUG=b:156447983
TEST=No timeout error when run "devbeep" in CLI.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The index of DRAM_STRAPS indicates to a specific DRAM characteristic
instead of a DRAM part number therefore update the existing DRAM SPD
binary to the naming by DRAM characteristic.
BUG=b:152019429
BRANCH=None
TEST=build the image and verify that coreboot log shows the correct SPD
info
Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update monolith root port settings to match those of the original BIOS.
MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced
Error reporting are enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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As per schematics configure headset interrupt as
edge both for ripto and volteer baseboard.
BUG=b:147085988
BRANCH=none
TEST=Build and boot ripto board. Test that jack functionality
is working fine and also confirm with evtest.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I8e1625140ccf55db8cb0fe3c039f1c31c01069b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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