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They default to zero already.
Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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They default to zero already.
Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Aligned text is easier to read.
Change-Id: I66a8efec3587649746bd56cd17eac2a06c9cc500
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As on most other boards, use tabs to indent the devicetree.
Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Let the linker trim unused net driver symbols when unused
in devicetree rather than being overly zealous in the Kconfig.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: Ie98d0f9f9b77cb9ee4e52f6c95b68bcbdd94f2cc
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Clean up devicetree as nothing special is needed here.
BUG=b:142769041
BRANCH=none
TEST=builds
Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Unlike laptops and some trash cans, desktop boards do not have a lid.
Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I496da344cc0d3845c308bca4d5da46d9ca6f88a7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ie8b9df7a64b45167de542182f3dfe6b320b9f2e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I023ce20b4144d782f22243911f845f6e28fdb2a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead
applied onto NID 0x1a. Fix that, so that it matches original Chromium
sources for the boards.
Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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These files are not headers.
Change-Id: Ibe6c9a96c1c4b0952a8d03b7a8b17869a66511f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Looks like the subvendor verb for codec #3 is erroneously using zero as
its codec number. Fix that.
Change-Id: I760533c229287627dd0548a06300c376e045302c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: Ifd1096cdf3700fa24ad8e5a701f48803650767bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I63e80953195a6c524392da42b268efe3012ed41b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37953
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Let coreboot know there is a NIC device on the end so
that the mac from vpd is set at early boot.
Properly configure the link-leds in devicetree s.t.
valid values are written out to the register at initialization.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See
* src/southbridge/intel/*/lpc.c
Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:
* src/southbridge/intel/*/lpc.c
Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extracted from live running machines running vendor firmware.
Change-Id: I5082af9349c25a5f1759ba00b3fbf8d18f8fde4d
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add Kconfig, panel delays extracted from VBT (and confirmed by Linux)
Test: build/boot Atlas with libgfxinit and Tianocore payload
Change-Id: I94c227cd4f020db719bf81118d983493752bb00f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adapted from Chromium commit b8dcb1a [Peppy: Update Memory IDs]
Add Hynix memory HMT425S6CFR6A support.
RAM_ID: 011 4GB Hynix HMT425S6CFR6A
RAM_ID: 111 2GB Hynix HMT425S6CFR6A
Original-Change-Id: I26d5c4ad00509e7823c325ee8391e0b18fee44d8
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1074849
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4d165f61b8a13e5ed025e9ddbc4330db88e2fa3d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.
Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.
Test: build/boot peppy on 4.18+ kernel, verify touchscreen working
Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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New FAN use NTN bearing, so tune DPTF parameters to satisfy
requirement
BUG=b:144370669
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6fbf0c80cd2421ce9a489c8923a97d860a11b545
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I7f159074c25a0fdfe2ee15024c1ed6c062ce75d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I169b16c99a864ecff54112bcc073f2c141c2009f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already.
Change-Id: I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The gnvs structure was zeroed out already in the following files:
* src/southbridge/intel/i82801ix/lpc.c (t400 and x200)
* src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58)
Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Remove acpi_update_thermal_table local function.
Change-Id: I4857348088feb8eaf1dd7f553c4efb29da8943cf
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We found the driver binding failure issue could be cleared with 100ms
of "reset_delay_ms". Needs further check with device vendor, anyway it
seems the IC need some time before communication after de-assertion of
reset.
BUG=b:129159369
BRANCH=firmware-hatch-12672.B
TEST=Verified driver bound successfully.
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a new sku for dragonair
BUG=b:146504217
TEST=emerge-hatch coreboot
Change-Id: I4492d65f35d3583df1606c5f2901228b3ae14e4a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I69c3b0b96fde8dc44a961c3d687f5aadbbdddde0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37644
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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related LTE GPIOs:
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:146843935
BRANCH=octopus
TEST=build and verify on the DUT with LTE
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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get_board_sku to smm stage.
fix Power_off section power sequence.
power_off_lte_module() should run in smm stage, add variant.c in smm stage.
also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage
and ramstage.
BUG=b:144327240
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Declare these sku IDs:
-SKU: 1 Foob, 1-cam, no touch, no pen.
-SKU: 9 Foob360, 2-cam, touch, pen.
BUG=b:145837644
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Iffcbb3f6f945ea299ff687a383a82b88dcd11ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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300ns
According to SI team and vendor request, need to tune I2C bus
0 data hold time more than 300ns
BUG=b:146163044
TEST=build firmware and measure I2C bus 0 data hold time
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37322
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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select SYSTEM_TYPE_CONVERTIBLE, which properly sets the
SMBIOS chassis type, and allows the OS driver to
recognize tablet mode capability
Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Adapted from Chromium commit 9522225e
[Kefka: Add memory SPD info for Hynix H9CCNNN8GTALAR-NUD]
Add current available ram_id to support Hynix H9CCNNN8GTALAR-NUD spd info.
RAM_ID: 0110 4GiB Hynix H9CCNNN8GTALAR-NUD
RAM_ID: 0111 2GiB Hynix H9CCNNN8GTALAR-NUD
Original-Change-Id: I48386ff3e5f80de94ea87359a09a5ec2577043b5
Original-Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/664517
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0ae76c4d8313246927bbc3f71b21f3611c89a6e3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update Eve's VBT from v211 to v221, and change the backlight
control type from PWM to VESA eDP/AUX. This allows the OS to
select the proper backlight control type for the panel.
Test: Eve backlight control now functional under Windows 10
(Linux requires some pending patches to fix)
Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921
TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The change applies the DPTF parameters received from the thermal team.
BUG=b:146540028
TEST=build and verified by thermal team.
Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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add new SKU ID below:
19 - Garg PVT (HDMI DB, Touch)
20 - Garg PVT (2A2C DB, Touch)
38 - Garg360 EVT (2A2C DB, touch, no stylues, rear camera)
BUG=b:146260545
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Ic74ce14db7060f3124c1a277eb3625ce0ff0b9f0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions
to wire SuperSpeed-capable ports to XHCI in its devicetree, causing
these ports being wired to the second EHCI, and only working as USB
2.0 ports. The missing register definitions are added to fix that.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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