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2019-04-04vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCHJoel Kitching
This option is duplicated in depthcharge: https://crrev.com/c/1545144 BUG=b:124141368, b:124192753, chromium:943150 TEST=make clean && make test-abuild CQ-DEPEND=CL:1545144 BRANCH=none Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-03mb/google/hatch: Enable Goodix Touch ScreenEric Lai
Enable Goodix touch screen. Follow GT7375P_Datasheet_Rev.0.1 BUG=b:124460799 BRANCH=None TEST=local build and tested with Goodix touch screen Change-Id: Ib204e6b77b87ba6c775cf38e572476dd9eb37d1d Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32134 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-03mb/google/sarien/variants/sarien: Update thermal configuration for DPTFJohn Su
Follow thermal table for second tunning. BUG=b:129509918 TEST=Built and tested on sarien system Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-04-02mb/google/poppy/variants/nami: update sku_ids for PantheonFrank Wu
The sku ids are updated for Pantheon. Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02mb/google/hatch: Change GPIO_E1 settingJohn Su
For HW require to change GPIO_E1. Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1). BUG=b:123730924 TEST=flash BIOS and make sure hatch boots up properly Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleepKrishna Prasad Bhat
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay resuming to S0. If this pad is not locked and platform was not initially designed for this functionality, malware could reconfigure this pads setting under OS (switch to Native3), which would make platform not able to resume until G3 is applied. To prevent misuse of this pad, re-configure this pad before entering S3 and S5 to guarantee that the pad configuration is correct. BUG=b:128686027 Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-01mb/aopen/dxplplusu: Remove redundant use of ACPI offset operatorElyes HAOUAS
Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01assert: Make dead_code() work at link-time instead of compile-timeJulius Werner
The dead_code() macro can be used to ensure that a certain code path is compile-time eliminated (e.g. if you want to make sure it's never executed for certain Kconfig combinations). Unfortunately, the current implementation via __attribute__((error)) hits only at the GCC level. This can catch code that can be compile-time eliminated based on state within the same file, but it cannot be used in cases where a certain library function is built but then garbage collected at link time. This patch improves the macro by relying solely on the linker finding an undefined reference. Unfortunately this makes the error message a little less expressive (can no longer pass a custom string), but it is still readable and one can add code comments next to the assertion to elaborate further if necessary Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01mb/google/sarien: Enable Bluetooth RF killLijian Zhao
Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:129375810 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Also confirm bluetooth itself is functional. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-01mb/google/hatch: Unlock GPIO padsKrishna Prasad Bhat
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. BUG=b:128686027 BRANCH=None TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register. localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080 0x00000000 localhost /sys/class/gpio # echo 212 > export Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-31mainboard/asus/p8h61-m_pro : Support TPM moduleSimon Newton
Select support in Kconfig and configure device in devicetree Tested with ASUS addon TPM modules, v1.2 (ASUS TPM-L FW3.19 rev1.02H) and v2.0 (ASUS TPM-L R2.0 rev1.00) using SeaBIOS and Linux OS Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7 Signed-off-by: Simon Newton <simon.newton@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29mb/google/arcada: Make bluetooth reset_gpio active lowMike Hsieh
Follow b:129375810 to set bluetooth reset_gpio as ACPI_GPIO_OUTPUT_ACTIVE_LOW BUG=b:129375810 TEST=Verified BT function on Arcada DVT1 system. Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I816eb2a76f642a2bb1702f38138bce7916334011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29mb/google/arcada: Make touchscreen IRQ level triggeredMike Hsieh
Touchscreen lost function after boot with stylus touching the screen BUG=b:128554235 Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I692fc6f245b7fade67862da4986a83d11a2cd51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32100 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29mb/google/hatch: Deassert EN_PP3300_WWAN during sleepMaulik V Vaghela
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when entering S5. This is the same fix in commit eeb475c5c for coral board. BUG=none BRANCH=none TEST=On hatch, Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28mb/google/sarien: Call EC romstage init functionDuncan Laurie
When in romstage call into the EC init function so it can send a progress code to the EC before memory training starts. BUG=b:127875364 TEST=boot with FSP debug and ensure EC does not try to turn off the system while it is still booting. Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28Mistral: Enable USB in romstageNitheesh Sekar
Enable USB support for mistral in romstage. TEST=build & run Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28chromeos: remove remaining dev switch referencesJoel Kitching
As part of chromium:942901, physical dev switch functionality is being deprecated. Remove remaining references as well as helper macros. BUG=chromium:942901 TEST=Build locally TEST=make clean && make test-abuild BRANCH=none Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-28mb/google/hatch/variants: Add DPTF based Fan controlSumeet Pawnikar
This adds DPTF based Fan speed control for CML based Hatch system. BUG=None BRANCH=None TEST=Built and tested fan speed with different temperatures Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28google/oak: Delete rowanEvan Green
Rowan board is dead, dissect it out of Oak. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=chromium:840888 BRANCH=none TEST=emerge-oak coreboot chromeos-bootimage CQ-DEPEND=CL:1538915,CL:*1087044 Change-Id: Ifb19fa0cd814853270847bc14fc21c841d905146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32061 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28mb/google/hatch: Initialize FPMCU_PCH_BOOT1Shelley Chen
In the latest hatch schematics, BOOT1 for the FP MCU is now connected to the AP. Configuring it to be the same as BOOT0. BUG=b:126455006 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-27mb/mainboard/google/hatch/variants: Set tcc_offset valueSumeet Pawnikar
Set tcc_offset value to 10C. It configures the Thermal Control Circuit (TCC) activation value to 90C. This prevents any abrupt thermal shutdown by taking early thermal throttling action when CPU temperature goes above 90C. Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27mb/google/poppy/variants/rammus: Support new onboard Micron memoryKane Chen
Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support. BUG=none BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-27mb/google/hatch: Add GPIO_A8 for Pen detect functionDtrain Hsu
Add GPIO_A8 for pen detect function. BUG=b:122765828 TEST=flash BIOS and using switch to verify GPIO_A8 value change. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be Reviewed-on: https://review.coreboot.org/c/coreboot/+/31815 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27mb/google/octopus/variants: Remove bipEvan Green
Remove bip, as it is no longer actively developed, and its EC overflowed storage, so the EC build is no longer viable. BUG=b:129283539 BRANCH=none TEST=emerge-octopus coreboot chromeos-bootimage CQ-DEPEND=CL:1538819,CL:*1086038 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ie9ffa704af3523908858d382e2c188422323550e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-27chromeos: update old boards to use lb_add_gpios notationJoel Kitching
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone. BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27vboot: deprecate physical dev switchJoel Kitching
Currently only two devices make use of physical dev switch: stumpy, lumpy Deprecate this switch. If these devices are flashed to ToT, they may still make use of virtual dev switch, activated via recovery screen. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25vboot: remove VBOOT_EC_SLOW_UPDATE Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1524806 BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1524806 BRANCH=none Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25mb/asus/{p5qc,p5q_pro}: Correct mapping of PCI-E 1x portsBill XIE
There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to the first three functions of 1c. Confirmed on a p5q_pro board. Change-Id: I779400494e27bf046996512d1f772311e6e4e091 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-25gale: add dev switch back as physical presence GPIOJoel Kitching
gale has a button which is essentially used as a "physical presence" button. Its only use is to emulate ^D or ^U on boot when the button is pressed. (See depthcharge src/board/gale/board.c) Previously (and currently in CrOS firmware branch) this GPIO was defined as the physical developer switch, and read as such in depthcharge. It was removed in cleanup patch CB:18980. Add the GPIO back as physical presence ("presence"), which will be read by depthcharge in CL:1532492. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-25mainboard/google/sarien: skip tpm check when !verstageJett Rink
The TPM driver isn't loaded in other stages but verstage so when we try to communicate with the TPM it fails. We don't need to communicate with it anyway since the TPM won't continue to tell us that recovery was requested, only the first query responds with the recovery request. BRANCH=none BUG=b:129150074,b:123360379 TEST=1)boot arcada without recovery and notice that the "tpm transaction failed" log lines are no longer present. 2) boot into recovery using the ESC refresh power key combination and verify that the recovery reason was "recovery button pressed" Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-24nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-24soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik
This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22mb/google/poppy/variants/atlas: DPTF tuning v2Puthikorn Voravootivat
We have more test data now so update the DPTF accordingly. * Change passive temp to 50/57/55/52 C * Change critical temp to 75C * All interval to 20 secs BUG=b:113101335 TEST=temp/perf looks better in thermal chamber test. Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22mb/google/hatch: Enable FP MCUShelley Chen
AP communicates with FP MCU through gspi1. BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/hatch: Add overridetree to hatch variantShelley Chen
Add serialio settings to hatch. Only applies to CML. BUG=b:128347800 BRANCH=None TEST=abuild Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/octopus: Add keyboard backlight support for bloogTony Huang
Bloog supports keyboard backlight feature, so enable the ASL code. BUG=b:127736039 BRANCH=octopus TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT. Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-22arch/mips: Fix <arch/mmio.h> prototypesKyösti Mälkki
These signatures need to be consistent across different architectures. Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-22mb/google/hatch: Add SX9310 SAR0 sensorEvan Green
Add SAR0, which is an SX9310. The schematics and layout have a second SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this is not populated. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=b:128540461 BRANCH=none TEST=Boot kernel with sx9310 driver, see it come up happily Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-22mb/google/hatch: Enable HUNG_TASK wake interruptEvan Green
Enable the HUNG_TASK as a wakeup host event, as it's used by S0ix failure detection to wake the system back up if a suspend to S0ix never asserted S0_SLP#. BUG=b:123716513 BRANCH=None TEST=Test S0ix on Hatch with appropriate EC and kernel changes. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I447211892df210af97e8df0380bab032b14cbee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32004 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21grunt: Mark RW_LEGACY as CBFSMathew King
Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate bootloaders, see https://crrev.com/c/1528550 and https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as CBFS in the fmap in order to work. All boards except for kahlee(grunt) have CBFS marked. BUG=b:128703316 TEST=Build and ran on grunt along with chromium patches on grunt and was able to list alternate bootloader with ctrl+l BRANCH=none Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21vboot: remove VBOOT_EC_EFS Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1523248 BUG=b:124141368, b:124192753, chromium:943511 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1523248, CL:1525647 BRANCH=none Change-Id: I8b3740c8301f9a193f4fce2c6492d9382730faa1 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31897 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21mb/siemens/mc_apl1: use comment in Kconfig.nameThomas Heijligen
Change-Id: I3c8791a0ed7b3bc670cf1433fa58f9b3d68e0b97 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-21mb/*/chromeos.c: Be explicit about code for ramstageKyösti Mälkki
Motivation is to reduce use of !__PRE_RAM__, it does not mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change. Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21mb/google/sarien: Add SKU for boards with signed ECDuncan Laurie
To support both boards with the same firmware add a SKU for each variant that is used to include the proper EC firmware image to match what the EC is expecting. BUG=b:119490232 TEST=tested by faking the EC response to ensure that the OS and firmware update tools are able to determine the correct model based on the value returned by the EC. Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20google/mistral: Implement board resetsanthosh hassan
Implement reset using PSHOLD. Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c Signed-off-by: Santhosh Hassan <sahassan@google.com> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 04:27:55 +0000