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2020-05-01mb/ocp/sonorapass: Add Sonora PassRyback Hung
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01mb/google/dedede: Fix crossystem wpsw_cur errorSubrata Banik
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/deltaur: Add BT reset gpioEric Lai
Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01mb/google/deltaur: Update USB/WWAN configIvy Jian
Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mainboard/google/kahlee: move specific setting to variantKevin Chiu
Separate specific setting to variant from baseboard. baseboard/romstage.c in current release is only utilized by careena, we could remove it from the rest of variant build. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-01mb/google/octopus/variants/bobba: Disable XHCI LFPS power managementSheng-Liang Pan
LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-05-01mb/google/volteer/malefor: Enable touch screenWilliam Wei
Enable Goodix touch screen and ensure it works properly. BUG=b:154191288 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the Goodix touch screen function. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598 Reviewed-by: Alex Levin <levinale@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/purism/librem_skl: Use ACPI backlight controlsBenjamin Doron
Enables ACPI backlight controls. Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-05-01mb/google/hatch/vr/puff: Add psys_pmax calculationTim Chen
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-01mb/google/dedede: Enable USB port for camera supportIan Feng
Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device treeMeera Ravindranath
This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-01src: Remove not used 'include <smbios.h>'Elyes HAOUAS
Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/google/dedede: Remove pad termination for RAM_STRAP_4Karthikeyan Ramasubramanian
The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01Helios: Update DPTF settings for smooth fan speed controlSumeet R Pawnikar
Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01mb/google/dedede: Enable camera support for waddledooPandya, Varshit B
BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: Add ACPI support for cameraPandya, Varshit B
1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI8856 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: add new variant for wheeliePeichao Wang
Add initial support for wheelie variant board. BUG=b:154664137 BRANCH=None TEST=build Change-Id: Id638e987f45c247dae824f221a38ccf32626572f Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/nightfury: Tune the usb2_port[0] strengthSeunghwan Kim
Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01mb/ocp/tiogapass: Update UPD IIO bifurcation at run-timeJohnny Lin
Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-30mb/cedarisland_crb: rework GPIOs configuration using macrosMaxim Polyakov
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-MMaxim Polyakov
We should be sure that after romstage the pads will be configured according to the config from gpio.h only. This patch sets the GPIO configuration from gpio.h using the soc/intel/common/gpio.c driver again in ramstage. [1] https://review.coreboot.org/c/coreboot/+/40730 Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-30mb/intel/cedarisland_crb: use common driver to configure GPIOMaxim Polyakov
According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-30mb/amd/padmelon: Remove PS/2 keyboard driver selectionPaul Menzel
Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the PS/2 keyboard themselves, so coreboot does not need to initialize it. Therefore, this option should not be hard-coded for the mainboard, and be left for the user to select. Change-Id: Ibfb7efa22c525e60399afc198af6632330faaac3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-30mb/pcengines/apu1: Remove PS/2 keyboard driver configurationPaul Menzel
Since commit 6aa8c5bc (drivers/pc80: Do not initialize PS2 keyboard by default), the Kconfig option `DRIVERS_PS2_KEYBOARD` already defaults to `n`. So, remove it here, as this option should be user selectable anyway depending on the payload. Change-Id: I3d08fb6bbb3e9d53fd2fed96f26679e8b1e73f8c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-30mb/purism/librem_bdw: Remove PS/2 keyboard driver selectionPaul Menzel
Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the PS/2 keyboard themselves, so coreboot does not need to initialize it. Therefore, this option should not be hard-coded for the mainboard, and be left for the user to select. Change-Id: Iac835d2e7a3232f8e5c76f10984ae3f172f9c0ca Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-30mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pinsBryantOu
Enable aspeed's function that port 80h direct to GPIO for LED display, refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's Application Design Guide, also configure GPIO to UART for output serial console messages. Tested=Check if port 80h LED debug card can display POST codes at early stage, and serial console can see the related messages. Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30mb/google/voteer: Enable DevSlp for SATA port1Wonkyu Kim
BUG=b:152893285 BRANCH=none TEST=Build and boot to OS volteer with Intel SATA and reboot from OS console Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-30mb/google/volteer: Create trondo variantDavid Wu
Create the trondo variant of the volteer reference board by copying the template files to a new directory named for the variant. BUG=b:154678884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TRONDO Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40686 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30mb/google/puff: update USB2 strengthTim Chen
Based on USB SI report to fine tune the strength for USB2 port0. BRANCH=none BUG=b:153590143 TEST=build and test USB2 port0 function works fine. Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-29mb/intel/tigerlake: Include TCSS power managementJohn Zhao
Include TCSS RTD3 into ACPI DSDT table. BUG=b:140290596 TEST=Booted to kernel and verified tcss xhci/pcierp/dma power state D3 entry/exit. Change-Id: I8cc5cfb572e15121059eb1fba41f931c59afbdf6 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-29mb/google/volteer: Include TCSS power managementJohn Zhao
Include TCSS RTD3 into ACPI DSDT table. BUG=b:140290596 TEST=Booted to kernel and verified tcss xhci/pcierp/dma power state D3 entry/exit. Change-Id: Iae31a29eb23f7370737d097dd401f4056b8b7052 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-29mb/google/octopus/variants/garg: update Garfour SKU IDTony Huang
SKUID: 49 - Garfour EVT (touch, TypeA DB) 50 - Garfour EVT (non-touch, HDMI DB) BUG=b:152861752 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-04-29soc/amd/hda: Move HDA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29mb/google/hatch/romstage_spd_smbus.c: Fix missing DIMM issueEdward O'Callaghan
Since `commit 0ee9b14c09c` the SPD array is set to NULL if no DIMM is present. This causes failure due to an unconditional use of `blk.spd_array[i]`, : i={0,1}. This validates the spd_array is non-NULL before use otherwise it sets the DIMM as not present. Puff fails boot with the following log: ``` ... SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb SPD: device width 8 bits, bus width 64 bits SPD: module size is 16384 MB (per channel) ASSERTION ERROR: file 'src/soc/intel/cannonlake/cnl_memcfg_init.c', line 47 ``` BUG=b:155220125 BRANCH=none TEST=none Change-Id: I5f47c849344951d53fa8c67e779b7c46d632d124 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40820 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29mb/google/volteer: Work around TPM issue by enabling GPIO PM in S0ixVenkata Krishna Nimmagadda
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on entry and on exit, it disables them. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:148892882 BRANCH=none TEST="Boot with this change on volteer proto1 and check for GPIO community config with debugger" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40261 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/volteer: move mipi_camera.asl to variants foldersNick Vaccaro
Moves mipi_camera.asl from mb/google/volteer/acpi/ to mb/google/volteer/variant/baseboard/include/baseboard/acpi/. Adds mipi_camera.asl to variant/[volteer|ripto]/include/acpi/. Adds new VARIANT_HAS_MIPI_CAMERA Kconfig option. Adds VARIANT_HAS_MIPI_CAMERA for volteer and ripto variants. BUG=b:154648941, b:154646959 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Ripto and Volteer to kernel. Change-Id: I2f28243dfb945857d26f27f07968a15a3eeb7a4f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40578 Reviewed-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/volteer: implement mainboard_get_dram_part_num()Nick Vaccaro
Implements mainboard_get_dram_part_num() to override dram part number with a part number read from CBI. BUG=b:146464098 TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer, boot and log into kernel, execute "mosys memory spd print id" and verify that the memory part number from the cbi gets displayed properly. Change-Id: I3a20691f601cb513ee0936c8d141233c3d06db3d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28mb/google/deltaur: Disable POWER_OFF_ON_CR50_UPDATEEric Lai
This is missing configuration of Wiloc projects. Following Wilco projects configuration. CB:32436 The power architecture on this platform is different than most of our other x86 devices and needs some special handling to ensure it powers up again after an EC reset. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Change H1 I2C speed to STANDARDEric Lai
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down the H1 I2C to avoid I2C error for short term. Error logs: Reading cr50 TPM mode I2C receive timeout I2C read failed: bus 3 addr 0x50 BUG=b:154310066 TEST=Check H1 has no I2C error occurring and can be updated by gsctool. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Enable PS/2 keyboardEric Lai
By default, the ACPI status method _STA returns false for the PS/2 keyboard and mouse device of the Wilco EC, so the OS does not enable it. Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K. BUG=b:154790509 TEST=Check Keyboard is functional under OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/intel/jasperlake_rvp: Configure GPIO for JSLRVPRonak Kanabar
We need to configure GSPI related gpios for external EC and TPM. Along with GSPI configuring gpios for LAN (power down), FSP_INT and PCH_INT. BUG=None BRANCH=None TEST=External EC card works and LAN is powered down. Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/intel/jasperlake_rvp: Update SMBIOS data for JslrvpMeera Ravindranath
1)Change Mainboard Part Number to jslrvp 2)Change Mainboard Family to Intel_jslrvp 3)Generate SMBIOS table and fill sku id information in SMBIOS BUG=None BRANCH=None TEST=Mosys works on jslrvp and Sku ID info is generated Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/octopus: add default non-ChromeOS FMAPMatt DeVillier
Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since GeminiLake-based devices like Octopus cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: Iebacbea5b3a782b2abf1d6e28acd21b87dc9402b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40596 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/octopus: Add VBT for ampton variantMatt DeVillier
Add VBT file, extracted from stock Google firmware, and select its use via Kconfig. Change-Id: I256c1c72d1d1e40ea9426fa717bfc4f9c950a91f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-27mb/google/deltaur: Enable DRIVERS_I2C_HID for TouchpadEric Lai
Cirque touchpad uses I2C_HID driver. BUG=b:152931802 TEST=Touch pad can work well in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27mb/google/deltaur: Move the code under domainEric Lai
Chip drivers not overrided if out of domain. Only device can get override, so move the code under domain. BUG=b:152924290,b:152931802 TEST=Touch screen and Touch pad can work well. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27mb/google/hatch/var/jinlon: Update DPTF parametersWisley Chen
The change applies the DPTF parameters received from the thermal team. 1. Set PL1 Min to 3W 2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec 3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points for tablet mode. 4. Update trigger points of CPU/TSR0/TSR1 BUG=b:154564062, b:154290855 BRANCH=hatch TEST=build and verified by thermal team. Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27mb/google/volteer: add touchscreen entry to VolteerAlex Levin
BUG=b:149588766 TEST=ELAN and Goodix touchscreen works. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I1c3e75eb03a8ab434ee58bf36a155f2255612083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 21:40:04 +0000