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2020-03-11mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-03-11mb/google/hatch: Add LP_4G_2133 SPDraymondchung
Add LPDDR3 4GB 2133MHz SPD file. BUG=b:149226871 TEST=Build and check cbfs has the spd.bin Change-Id: I1598774a87eecc76082286540beadaa3c26eda69 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/google/volteer: Enable pcie rp11 for optaneVenkata Krishna Nimmagadda
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins. Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode. BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer' Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428 Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/google/volteer: Disable WWAN PCIeAlex Levin
Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer. BUG=b:146226689 BRANCH=none TEST=lsusb shows WWAN device Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-11mb/intel/tglrvp: sync up variant folders with latest up3Wonkyu Kim
During intial UP4 patch, below UP3 patches merged which should be applied for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge these patches to UP4 BUG=none BRANCH=none TEST=Build TGL UP4 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2020-03-11mb/biostar/am1ml: Remove old reference to olivehillplusElyes HAOUAS
Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11mb/asus/am1i-a: Remove old reference to olivehillplusElyes HAOUAS
Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11mb/amd/olivehillplus: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/amd/bettong: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: I1bce09ba5041a6636f900de611846467653f35a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/amd/db-ft3b-lc: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/amd/lamar: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/google/puff: Enable cros_ec_keyb deviceKangheui Won
This is required to transmit button information from EC to kernel. BUG=b:150830342 BRANCH=None TEST=firmware_ECPowerButton test passes on puff Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-03-10mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv configPraveen Hodagatta Pranesh
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10src: Remove unneeded 'include <arch/cache.h>'Elyes HAOUAS
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binariesNico Huber
If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/libretrend/lt1000: Add Libretrend LT1000 mainboardMichał Żygowski
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/protectli/vault_kbl: Add FW6 supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/google/volteer: set TcssXhciEn to 1Brandon Breitenstein
BUG=144874778 TEST=Built with Volteer recipe and verified USB functionality Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/dedede: Add PCIe Root Port ConfigurationKarthikeyan Ramasubramanian
Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Configure EDP_HPD GPIOKarthikeyan Ramasubramanian
This enables display for use by payload. TEST=Build and boot the mainboard. Ensure that the screens displayed by payload are visible. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/dedede: Configure EC <-> AP GPIOsKarthikeyan Ramasubramanian
BUG=b:150869661 TEST=Build and boot the mainboard. Trigger apreset from EC console. Trigger reboot from AP console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Add GPIO listKarthikeyan Ramasubramanian
Leave all the GPIOs in not connected state so that they can be configured depending on the use-case. This is done to park the GPIOs in a known safe state. This will also help to ensure that the required GPIOs are configured when the concerned use-cases are enabled. Below GPIOs are configured in Native Function 1 and are required for boot-up. * VCCIN_AUX_VID0 * VCCIN_AUX_VID1 * AP_SLP_S0_L * PLT_RST_L * CPU_C10_GATE_L * GPDs BUG=None TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/volteer: Enable FPMCU on volteerAlex Levin
BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/volteer: change two gpio settingsNick Vaccaro
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment BUG=b:144933687, b:148179954 BRANCH=none TEST=none Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/protectli/vault: Add FW2B and FW4B Braswell based boards supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to clobber the registers with garbage in ramstage. Tested, my Asus P5G41T-M LX still boots and it does not need a full reset on almost every reboot. Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/asus/p5g41t-m_lx: Correct GPIO directionAngel Pons
Not all GPIO4 pins on the SuperIO are configured as outputs. Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-09mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage. Tested, my Asus P5QPL-AM still boots. Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/intel/tglrvp: Add memory config for Tiger Lake UP4Srinidhi N Kaushik
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/intel/tglrvp: Add TGL UP4 RVPWonkyu Kim
Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb/google/volteer: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi. BUG=none BRANCH=none TEST=Build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-07mb/intel/tglrvp: Add pin mux for CameraWonkyu Kim
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera Simple test method to check camera: capture image by below commands from OS console >media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]" >media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]" >yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10 $(media-ctl -e "Intel IPU6 CSI2 BE capture") Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I4fa89dc1ad4196a61bb0cdfaa0d59dfe4c6fff12 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb/intel/tglrvp: Update display ports for RVPWonkyu Kim
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229 Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb/google/volteer: add samsung-K4UBE3D4AA-MGCR SPDNick Vaccaro
Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1. BUG=b:148182234 BRANCH=none TEST=none Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-07mb/lenovo/*/devicetree: Declare device in one line if possiblePeter Lemenkov
Change-Id: I708281f7861110e4abc02948c74affad9fa37053 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07chromeos: stop sharing write protect GPIO with depthchargeJoel Kitching
wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variantAngel Pons
Took less than 30 minutes, and booted on the first try :) Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-07mb/asus/p8z77-v_lx2: Add new mainboardAngel Pons
This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - SeaBIOS to boot Arch Linux Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-07mb/intel/tglrvp: Add fixed SKUID to SMBIOS tablesWonkyu Kim
Report fixed SKUID (255) to support mosys. BUG=none BRANCH=none TEST=boot tigerlake rvp board and check mosys and SKUID from smbios Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I7a5beed307fd7880a6af127b2dcd06e93e50547d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39269 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/google/kahlee/nuwani: Create Nuwani variantPeichao Wang
This commit creates a nuwani variant for Grunt. The initial settings override the baseboard was copied from variant treeya. BUG=b:144890301 TEST=emerge-grunt coreboot Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mainboard/ocp: Add support for OCP platform TiogaPassJonathan Zhang
OCP platform Tiogapass is a 2-socket server platform, which is based on a chipset including Intel Skylake-SP processors and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon Scalable Processor family. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset is tested on a Tiogapass board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets, 18 cores, 2 thread per core); ssh command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Towards successful gerrit buildbot build, note that: * microcode is in coreboot intel-microcode submodule repo. * IFD binary is included in this patch. * Dummy ME binary is used, as it may take long time for Intel ME binary to be available in public domain. * Fake FSP binary is used, as at this moment the SKX-SP FSP binary is not going to be available in public domain. Known issues (Not intend to address in this initial support for Xeon-SP processors): * c6 state is not supported. * dsdt table is not fully populated, such as processor/socket devices, some PCIe devices. * SMM handlers are not added. Following are some command execution with CentOS booted from local SATA disk: [root@localhost ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 72 On-line CPU(s) list: 0-71 Thread(s) per core: 2 Core(s) per socket: 18 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz Stepping: 4 CPU MHz: 140.415 BogoMIPS: 4626.46 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0-17,36-53 NUMA node1 CPU(s): 18-35,54-71 [root@localhost ~]# ifconfig eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255 inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link> inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global> ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet) RX packets 84249 bytes 6371591 (6.0 MiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 8418 bytes 748781 (731.2 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1000 (Local Loopback) RX packets 613 bytes 63906 (62.4 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 613 bytes 63906 (62.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 [root@localhost ~]# cbmem 36 entries total: // Lines were cut to avoid checkpatch.pl warnings Total Time: 96,243,882,140,175,829 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-06mb/lenovo/x230: List Lenovo X230t convertible/tablet as variantPeter Lemenkov
Lenovo ThinkPad X230t Convertible Laptop works well with X230 default image (see CB:34361). Change-Id: Ib0a73fd551f0d26c789d3fd13541b2d1571742cb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38482 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/lenovo: Remove thermal.h headerPeter Lemenkov
We include it only in one file. So let's simplify everything and do like autoport does. Change-Id: I71f092ed7582b4931122d72f41d0b42a7569b96e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-06mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGLSrinidhi N Kaushik
Add support for Max98373 speaker amp & ALC5682 headset codec BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-06mb/up/squared: move USB config to device treeMaxim Polyakov
Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/up/squared: remove NpkEn option from romstageMaxim Polyakov
There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06mb/google/volteer: add new ripto variantNick Vaccaro
Add a new ripto variant based off of the volteer baseboard design. BUG=b:148385924, b:150810535 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image and verify ripto boots to the kernel. Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-23 11:51:51 +0000