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2015-03-04t132: Add shared romstageAaron Durbin
There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add dram init codeFurquan Shaikh
Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add support for basic romstageFurquan Shaikh
Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh
Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh
Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-26mainboard/asus/kfsn4-dre: Enable W83793 fan controllerTimothy Pearson
The Winbond W83793 fan controller is not automatically configured correctly on power application, leading to abnormal, and in some cases random, fan behaviour. This commit enables the controller and sets sane default values. TEST: Booted mainboard and verified that the correct number of fan speed sensors were visible from hwmon under Linux. Also verified that, unlike before, the CPU fans were running at a high enough speed to properly cool the CPUs. Verified the 8 fan outputs under direct control of the W83793 device. Verified voltage and temperature sensors and limits via output of the 'sensors' command. Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8503 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-25rush: Correct version field to match t132Aaron Durbin
The version field for t132 cpus is 0x00130001. Update it to the correct version. BUG=chrome-os-partner:29882 BRANCH=None TEST=Built and was able to see serial with subsequent changes. Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205435 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a Reviewed-on: http://review.coreboot.org/8467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24(bakersport|bayleybay)_fsp: Do not force a default loglevelAlexandru Gagniuc
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and should not be overriden by any other part of the tree. As such, remove the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards. Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8486 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24mainboard: Do not redefine CONSOLE_POST Kconfig variableAlexandru Gagniuc
This option is already defined in console/Kconfig, and is intended to be controlled by the user. Only six boards in the entire tree redefined it, so remove the definition from those boards. Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8457 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24soc/fsp_baytrail: Fix use of microcode-related Kconfig variablesAlexandru Gagniuc
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs with updateable microcode (except AGESA) load microcode from CBFS. CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set based on user's choice in the microcode menu and should not be changed directly. Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly interferes with the microcode mechanism, remove selection of CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the microcode mechanism consistent with other CPUs in the tree. This incorrect usage of the Kconfig variables was hiding the fact that some of the microcode files present in fsp_baytrail/microcode_blob.c were not present in the tree. Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-23pcengines/apu1: Fix 0:15.x PCIe root portsKyösti Mälkki
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fix and clean up devicetreeKyösti Mälkki
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware. Disable 0:14.1 IDE controller, as it would only be used with SATA ports 4 and 5 that are not populated with connectors in the hardware. Disable 0:14.2 HD audio, as it is not implemented in the hardware Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller are not populated in the hardware. Fix some alignment and whitespace. To my knowledge these changes are not included with SAGE release pcengines.apu_139_osp.tar.gz, but that tarball does not contain either devicetree.cb or a pre-compiled static.c file so I cannot tell for sure. Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8328 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fix PCI device 16 interruptsKyösti Mälkki
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed in PIC mode. The only affected peripheral was the SD card reader. This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz. Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8327 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-02-23pcengines/apu1: Implement board GPIOsKyösti Mälkki
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: New board PC Engines APU1Kyösti Mälkki
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL: SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4 pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files. Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8325 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fork of amd/persimmonKyösti Mälkki
Drop persimmon customization for superio, azalia, PCI-e reset etc. Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20AMD amdfam10: Always have HT3_SUPPORTKyösti Mälkki
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-17google/rush: Add BCT support in mainboard rushFurquan Shaikh
Changes might be required for .bct files as we get to know more. Pulling in files from mainboard nyan for now BUG=None BRANCH=None TEST=Compiles successfully for rush Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/203144 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8412 Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-16mainboard/asus/kfsn4-dre: Add HT speed limit to NVRAMTimothy Pearson
Change-Id: Ia4829447835dd26381185c586eaac210dc0591d9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8463 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16mainboard/cmos: Kill off unused boot_* parametersTimothy Pearson
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Move ECC variables out of fallback mechanism byteTimothy Pearson
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8458 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-16mainboard/amd/amdfam10: Update AMD K10 socket F NVRAM layout filesTimothy Pearson
This removes spurious K8 options and adds appropriate K10 options. File content taken from the functional K10 ASUS KFSN4-DRE board. Change-Id: I237bb139056f39f21416268cb52d24c5bc5f111d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8456 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/asus/kfsn4-dre: Remove hard-coded ECC scrub rateTimothy Pearson
Change-Id: I6ccf44645dabf8ac3674f40d3c5cbcf694aa6237 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8441 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/asus/kfsn4-dre: Add memory interleave options to NVRAMTimothy Pearson
These values were originally hard-coded in the AMD MCT wrapper. Change-Id: I12056d38d5348e70a44c192385e22e715e207792 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/asus/kfsn4-dre: Add ECC redirection to NVRAMTimothy Pearson
Change-Id: Ie7a73a5962e61585ebc427005e72715c8da4e0ac Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8451 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/asus/kfsn4-dre: Add ECC scrub rate to NVRAMTimothy Pearson
Change-Id: Iaece709f521aaf6689b71bc0c71606847c3e1e4e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8439 Tested-by: build bot (Jenkins)
2015-02-16mainboard/asus/kfsn4-dre: Add default NVRAM settingsTimothy Pearson
Change-Id: Ic86104d6e7811b0bda9279411db84f464324994a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8450 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/asus/kfsn4-dre: Fix invalid CMOS enumsTimothy Pearson
Change-Id: Id837445f346e9ab0218ccca12794b519a8a71c0d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15hp/pavilion_m6_1035dx: Provide CMOS defaultsAlexandru Gagniuc
TEST: Boot with corrupted CMOS and make sure console level defaults to SPEW, instead of 0, and that cbmem console is not empty. Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8379 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configurationKyösti Mälkki
A set of pins can be configured for GPIO or (parallel) PCI bridge use. When requested configuration is 0:14.4 enabled, register programming must be done before attempting to enumerate devices behind the bridge. When requested configuration is 0:14.4 disabled, we must not even temporarily enable pins for PCI use to avoid spurious GPIO state changes. As our PCI subsystem currently does not configure visible PCI bridges that are marked disabled, we cannot mark 0:14.4 disabled just yet but need to handle pcengines/apu1 as a special case. Drop related dead code. Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14AGESA fam10 fam12 fam15: Always have HT3_SUPPORTKyösti Mälkki
Keep the slower HyperTransport configuration for a possible reference in fam15 boards. Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-12AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctlyPaul Menzel
Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5101 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-11asus/m4a785/Kconfig: Add vgabios PCI idNicolas Reinecke
The PCI id defaults to 1106,3230 -> via chrome 9 ... Tested on the board. Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVIDTimothy Pearson
This resolves an issue on Shanghai dual CPU configurations where the APs on node 0 would not start. Single CPU configurations are unaffected by this issue. TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified proper BSP/AP start and microcode patch levels. Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8397 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-10lenovo/x200: Increase default CBFS_SIZE to 2 MiBMichał Masłowski
The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB flash variants. Let's allow using the whole region instead of the gm45 default of 1 MiB. Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: http://review.coreboot.org/8392 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-09Intel FSP platforms: Fix timestampsKyösti Mälkki
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8024 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-08lenovo/t430s: Add new port.Nicolas Reinecke
The port is based on the x230 / t530. Tested - is in active use. Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8359 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06mainboards/asus/kfsn4-dre: Indicate native text mode init supportTimothy Pearson
Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8369 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05mainboards/asus/kfsn4-dre: Enable native VGA initializationTimothy Pearson
Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05newisys/khepri broadcom/blast: Drop duplicate entry in KconfigKyösti Mälkki
Keep the value that is listed first, it also the one with a more recent change. Change-Id: I0336c962544d75f94512563c08f280aa43c7a175 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8336 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-03amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selectionKyösti Mälkki
Include microcode updates in CBFS for every CPU revision the platform can support, as changing to different CPU revision should not require a coreboot rebuild. This increases CBFS usage from 2 kB to 14 kB. Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4521 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-01winent/mb6047: switch to CAR version of ck804 early_setup.cJonathan A. Kollasch
Change-Id: I9b45b7fbd862a5600ead7ad4e623a8a87ae364aa Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8319 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01winent/mb6047: clean up includes in acpi_tables.cJonathan A. Kollasch
Change-Id: I63bdc856fa4232cd66ff2e48e39c2cdb97bb88d3 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8316 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01winent/mb6047: use correct ACPI SCI interrupt triggerJonathan A. Kollasch
Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8315 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-02-01winent/mb6047: drop inaccurate comment in acpi_tables.cJonathan A. Kollasch
Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8314 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.Vladimir Serbinenko
Fixes USB3 ports degraded to USB2 speeds. Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/8313 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-31asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devicesTimothy Pearson
Test: Single Opteron 2419 with 1GB RAM in slot A1 Booted Ubuntu Linux 14.04 and verified all 6 cores were visible Brief stress test of all 6 cores simultaneously Verified proper ACPI power states for all 6 cores Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8311 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-28 11:29:33 +0000