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2019-11-20nb/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-30nb/amd/amdht: Use standard coreboot assertionsJacob Garber
The amdht code currently relies on an idiosyncratic ASSERT() macro, which actually doesn't do anything right now, and even it did would only print a janky error message. Replace this with the normal ASSERT() macro from <assert.h>. The default behaviour now is to print an error message but do nothing else, and failed assertions will only halt if you enable FATAL_ASSERT, in which case, well, you asked for it. Change-Id: I6db7565171a345f9afbc9fb37cff8fda58f942df Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402076 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29src/northbridge: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-19src: Add required space after "switch"Elyes HAOUAS
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-08src: Replace common MSR addresses with macrosElyes HAOUAS
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-23src: Typo fix (cosmetic)Peter Lemenkov
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-08nb/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07nb/amd/amdht: Use variable for function namePaul Menzel
One very long line has to be wrapped to be shorter than 80 characters to satisfy the lint scripts. Note, that this gets rid of the brackets (). Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-01-26amd/amdht: Fix format security errorsPaul Menzel
Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat -Wformat-security`, causing errors similar like the one below. ``` CC romstage/northbridge/amd/amdht/ht_wrapper.o src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify': src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security] printk(log_level, event_class_string_decodes[evtClass]); ^ […] ``` Fix that, by explicitly using a format string. TEST=Built and booted on ASUS KGPE-D16. [1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for "fprintf, error: format not a string literal and no format arguments [-Werror=format-security" [2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609. Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18208 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-13northbridge/amd/amdht: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdht. Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16468 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)Damien Zammit
Change-Id: I96d695ed10176276116fcf3a2b77605fb3f2d5db Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13710 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04northbridge/amd/amdht: Reduce excessive romstage array sizeTimothy Pearson
Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12573 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUsTimothy Pearson
The existing code re-used the Family 10h XCS buffer setup on Family 15h CPUs, which set incorrect values leading to random system lockups. Use the Family 15h XCS buffer setup shown in the BKDG. Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24northbridge/amd/amdht: Add isochronous setup supportTimothy Pearson
The coherent fabric on all Family 10h/15h devices supports isochronous mode, which is required for IOMMU operation. Add initial support for isochronous operation. Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20northbridge/amd/amdht: Add comment for HT Freq write orderingTimothy Pearson
The BKDG is not correct regarding HT Freq write ordering; indicate this in a comment to avoid confusion. Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12030 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12021 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-24cpu/amd: Add initial support for AMD Socket G34 processorsTimothy Pearson
Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11940 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-08-30Kconfig: Remove EXPERT modeAlexandru Gagniuc
After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-15northbridge/amd/amdht/h3finit.c: Fix boot failureTimothy Pearson
GIT hash 586d6e introduced a regression that causes boot failure with an f0011449 AMD stop code. Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8685 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-13northbridge/amd/amdht: Allow mainboards to set HT frequency limitTimothy Pearson
This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16northbridge/amd/amdht: Get maximum HT link frequency from NVRAMTimothy Pearson
This patch allows the user to set a maximum HT link frequency in NVRAM, paralleling a similar option available in the proprietary BIOS on some mainboards. Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8462 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16northbridge/amd/amdfam10: Remove HT link frequency from Kconfig menuTimothy Pearson
Change-Id: I48d2cda330d8e8f1e58bc670e4e898479216e576 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8461 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28northbridge/amd/amdht: Initialize variable `currentBUID`Timothy Pearson
Fix uninitialized variable when manual non-coherent BUID selection is used. Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8267 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27amd/amdht: Compile in multiprocessor support when selectedTimothy Pearson
Fix multiprocessor support not being compiled in when selected via Kconfig on AMD systems. Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8268 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-08northbridge/amd: Doxygen fixesMartin Roth
- Add missing parameter names in several files - remove parameter types in several files - remove lines from doxygen documentation. These should be outside the doxygen comments. - Some of the comments shouldn't have been doxygen style. Turn these into regular non-doxygen comments. Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8153 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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