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2018-11-05amd/mtrr: Fix IORR MTRRElyes HAOUAS
IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-25nb/amd/amdmct: Remove another currently unused tableJonathan Neuschäfer
This fixes a warning that the new toolchain generates. Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24nb/amd/amdmct: Remove two currently unused tablesJonathan Neuschäfer
This fixes warnings that the new toolchain generates. Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18058 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-11-09nb/amd/amdmct/mct: Remove commented codeElyes HAOUAS
Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17172 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-16nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slotsTimothy Pearson
The current code did not define the number of DIMM slots on the mainboard, which lead to incorrect configuration values and occassional training failure. Add preliminary support for DIMM slot count configuration. Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-14northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tablesTimothy Pearson
Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-26northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalizationTimothy Pearson
The native AMD DDR3 memory initialization code was riddled with numerous errors and was missing critical configuration code segments; this made it so that DDR3 memory did not function on most AMD boards. This patch corrects enough of the DDR3 initialization such that UDIMMs can be used on most channels of G34 Opteron boards. Further work is needed to fix the broken RDIMM code and remaining UDIMM issues. Change-Id: Iab690db769e820600693ad1170085623b177b94e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11941 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-23northbridge/amd/amdmct: Fix Family 15h detectionTimothy Pearson
Change-Id: I3623f8945bd62b7050ec609934f96543552c792b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12018 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
1.) Allow MCT information structures to be copied to cbmem. 2.) Retrieve DIMM vendor, model, and serial information. 3.) Allow maximum installable memory to be set via devicetree. Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9137 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-01northbridge/amd/amdmct: Pack MCT and DCT info structsTimothy Pearson
This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and laterTimothy Pearson
The BKDG for K10 revision D and later processors recommends a smaller MCT burst write queue depth when using unganged memory. TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431 processors. Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-15northbridge/amd/amdmct: Fix FTBFS with node interleaving enabledTimothy Pearson
This fixes errors of the form: error: 'Dct0MemSize' may be used uninitialized in this function Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8455 Tested-by: build bot (Jenkins)
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the northbridge code to use printk() on all non-ROMCC boards. Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7856 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-08northbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6210 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23northbridge/amd/amdmct: Superfluous parenthesis in if-statementsEdward O'Callaghan
Remove superfluous parenthesis found in some if-statements, spotted by Clang. Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5817 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22northbridge/amd/amdmct/mct: Initialize variables at the eolEdward O'Callaghan
Spotted by Clang Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5816 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-03This patch sets max freq defaults for ddr2 and ddr3for fam10.Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add AMD C32 support.Zheng Bao
It is based on other existing Fam10 code. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-02More explicite and straight way to set seed.Zheng Bao
The read-modify-write wasn't needed. This is easier to understand. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13Trivial. Clean up code and add some comments.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09Trivial. Spell checking.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09Trivial. Spell checking.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08Trivial. Spell checking.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08Trivial. Fix the typo.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Trivial. Re-indent the code.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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