summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdmct
AgeCommit message (Expand)Author
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-01-20For Cx, each ChipSel need to be sent MR command.Zheng Bao
2011-01-17The code is tested on my board with register DIMMs. More tests need to beZheng Bao
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
2010-12-02More explicite and straight way to set seed.Zheng Bao
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
2010-10-13Trivial. Clean up code and add some comments.Zheng Bao
2010-10-09Trivial. Spell checking.Zheng Bao
2010-10-09Trivial. Spell checking.Zheng Bao
2010-10-08Trivial. Spell checking.Zheng Bao
2010-10-08Trivial. Fix the typo.Zheng Bao
2010-10-01Trivial. Re-indent the code.Zheng Bao
2010-09-28Trivial. re-Indent the code.Zheng Bao
2010-09-27Obviously missing brackets.Xavi Drudis Ferran
2010-09-21Complete the code which was missing.Zheng Bao
2010-09-21Fix the typo. Field DisAutoRefresh is in DramTimngHi.Zheng Bao
2010-09-09Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch
2010-09-09Also improve boot time on AMD for the DDR3 code path.Arne Georg Gleditsch
2010-09-09Apparently, it's not crucial to clear this at the exact moment we switchArne Georg Gleditsch
2010-09-05Trivial. Currently the max frequency is preset as 400Mhz. We need to set aZheng Bao
2010-09-04AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.Kerry She
2010-08-31Get Byte65/66 for register manufacture ID code. RegMan1Present willZheng Bao
2010-08-30Multi-DIMMS on AMD ddr2 MCT channel B fixed.Kerry She
2010-08-30Multi-DIMMS on AMD ddr3 MCT channel B works.Kerry She
2010-08-30Trivial syntax correction of AMD mct_ddr3 dir.Kerry She
2010-08-22documented workaround erratum 414, seeXavi Drudis Ferran
2010-08-22documented workaround erratum 372, seeXavi Drudis Ferran
2010-08-22Include RB_C3 in erratum 346Xavi Drudis Ferran
2010-08-22Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.Xavi Drudis Ferran
2010-07-08Fix all warnings in the tree Stefan Reinauer
2010-07-08get rid of even more fam10 and k8 warnings.Stefan Reinauer
2010-05-09Move includes to where they are needed. This allows to simplifyPatrick Georgi
2010-04-30Get rid of a few more warnings.Myles Watson
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
2010-04-24Trivial. Fix a space to tab.Zheng Bao
2010-04-23DDR3 support for AMD Fam10.Zheng Bao
2010-04-16zero warnings days: unify mp tables. fix warnings.Stefan Reinauer
2010-04-15Remove a few more warnings from fam10.Myles Watson
2010-04-14fix a case where the fam10 code would overwrite parts of a struct.Stefan Reinauer
2010-04-14HWHoleSz must be u32...Stefan Reinauer
2010-04-09zero warnings days.Stefan Reinauer
2010-04-08Cosmetically make init_cpus more similar for fam10 and K8.Myles Watson
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
2010-03-10The following patch implements Opteron Fam 10 rev D (aka Istanbul)Arne Georg Gleditsch
2009-09-14Use the coreboot pci config read/write functions instead of direct cf8/cfcMarc Jones
2009-08-25Without this patch, if we only got a DIMM in Channel B, memory can not beZheng Bao
2009-08-24This patch is about the DA-C2 and RB-C2. Chip with install processorZheng Bao
2009-08-19The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instea...Zheng Bao
2009-07-17This is an obvious bug which I overlooked when I worked on the AM2r2Zheng Bao
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 10:53:01 +0000