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path: root/src/northbridge/amd/amdmct
AgeCommit message (Expand)Author
2009-09-14Use the coreboot pci config read/write functions instead of direct cf8/cfcMarc Jones
2009-08-25Without this patch, if we only got a DIMM in Channel B, memory can not beZheng Bao
2009-08-24This patch is about the DA-C2 and RB-C2. Chip with install processorZheng Bao
2009-08-19The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instea...Zheng Bao
2009-07-17This is an obvious bug which I overlooked when I worked on the AM2r2Zheng Bao
2009-07-01Add AMD family 10 AM2r2 support.Zheng Bao
2009-06-06Fix for Erratum 350 for AMD Fam10h CPUs.Marco Schmidt
2009-05-14Update equivalent processor revision ID to load latest microcode patches andMarc Jones
2008-12-05Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>Stefan Reinauer
2008-07-23Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).Marc Jones
2008-04-25Remove inline from FAM10 CPU initialization functions.Marc Jones
2008-04-22Add early MSR and PCI register initialization. Marc Jones
2008-04-11Bring Fam10 memory controller init up to date with the latest AMD BKDGMarc Jones (marc.jones
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
2007-12-19Initial AMD Barcelona support for rev Bx.Marc Jones