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path: root/src/northbridge/amd/pi/agesawrapper.c
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2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-15nb/amd/pi/00730F01: Initialize IOMMU deviceKyösti Mälkki
Change-Id: I12d3ed35770ee06626f884db23004652084c88c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15186 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-09-26AGESA: Avoid cpuRegisters.h includeKyösti Mälkki
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move agesawrapper_laterunaptask()Kyösti Mälkki
Change-Id: I916d808d1b2ecc4b70b5dfebff62c4a18119f157 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Refactor eventlog read loopKyösti Mälkki
Also avoid infinite loop. Change-Id: I7571f9efdc2bf0335788136b8c56e9290581d748 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Use common handler for ACPI tablesKyösti Mälkki
Change-Id: I2d6ab1026f1105f1fea97682442a169409248c39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17binaryPI: Switch to agesa/def_callouts.cKyösti Mälkki
Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
Change-Id: I0f78cb275ecad732f81c609564a0640f03d2559e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-05-30binaryPI: Move EmptyHeap() callKyösti Mälkki
Specification says to do CAR teardown as part of AmdInitPost(). Move initializing the final AGESA heap storage to AmdInitEnv() so that its work is not lost even if AMD_DISABLE_STACK does invalidation without writeback. Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18binaryPI: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27cpu/amd/pi: Change wrapper to use config optionMarshall Dawson
Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-02agesawrapper: Fix endless loop on bettongRicardo Ribalda Delgado
AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17924 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-09amd/pi: Make BottomIo position configurableRicardo Ribalda Delgado
Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-10-04src/northbridge: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16863 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-09AMD binaryPI: Allow fine-tuning platform memory configurationKyösti Mälkki
The RDK amd/db-ft3b-lc board will use this for on-board DDR3. Change-Id: I2ffd38e7e949d3a60487e91188ddaab04b03d4b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12358 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2015-11-06AMD binaryPI BiosCallouts: Remove castKyösti Mälkki
This cast only hides errors in matching the API properly. Change-Id: I9b878ab997b8ff087a7209f94522646b10b94bf6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12271 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-08-31AMD Bettong: Lower the TOM to give more MMIO spacezbao
Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21Revert "northbridge/amd/pi: Add support for memory settings"Marc Jones
This is breaking the build right now. Reapply once the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f Reviewed-on: http://review.coreboot.org/11020 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-20northbridge/amd/pi: Add support for memory settingsDave Frodin
This adds support for binarypi based boards that have to make adjustments to the memory configuration settings. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10672 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interfaceWANG Siyuan
PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h /// PCIe PSPP Power policy typedef enum { PsppDisabled, ///< PSPP disabled PsppPerformance = 1, ///< Performance PsppBalanceHigh, ///< Balance-High PsppBalanceLow, ///< Balance-Low PsppPowerSaving, ///< Power Saving MaxPspp ///< Max Pspp for boundary check } PCIE_PSPP_POLICY; Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10461 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-22AMD Merlin Falcon: Add northbridge files for new AMD processorWANG Siyuan
Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot. Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10419 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-13amd/pi: Move AGESA cbfs access into the wrapperMarc Jones
The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-03-16northbridge/amd/pi: Create common agesawrapper.cDave Frodin
This removes the mainboard agesawrapper.c file from binarypi based boards and creates a common one. Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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