Age | Commit message (Expand) | Author |
2016-05-09 | nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure | Timothy Pearson |
2016-05-09 | nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h | Timothy Pearson |
2016-05-06 | amd/gx2 + amd/lx: Fix shift overflow issue | Stefan Reinauer |
2016-05-02 | nb/amd/mct_ddr3: Only initialize ECC bits once | Timothy Pearson |
2016-05-01 | nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h | Timothy Pearson |
2016-05-01 | nb/amd/mct_ddr3: Stop receiver enable cycle training after window found | Timothy Pearson |
2016-05-01 | nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0 | Timothy Pearson |
2016-05-01 | nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4 | Timothy Pearson |
2016-05-01 | nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h | Timothy Pearson |
2016-04-28 | nb/amd/mct_ddr3: Restart system on training failure instead of using die() | Timothy Pearson |
2016-04-26 | nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines | Timothy Pearson |
2016-04-26 | nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup | Timothy Pearson |
2016-04-25 | nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change | Timothy Pearson |
2016-04-22 | Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" | Timothy Pearson |
2016-04-22 | nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change | Timothy Pearson |
2016-04-22 | nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs | Timothy Pearson |
2016-04-22 | nb/amd/mct_ddr3: Run fence training on each node after memory clock change | Timothy Pearson |
2016-04-20 | AMD CIMX: Drop unused code | Kyösti Mälkki |
2016-04-16 | northbridge/amd/{lx,gx2}: remove immediate accesses of 0 | Patrick Georgi |
2016-04-13 | amd/agesa/family12/dimmSpd.c: Indent (tab) fix | Edward O'Callaghan |
2016-04-11 | and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignment | Timothy Pearson |
2016-04-11 | nb/amd/amdfam10: Write MCT variables to flash after PCI configuration | Timothy Pearson |
2016-04-08 | Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed" | Timothy Pearson |
2016-04-08 | nb/amd/mct_ddr3: Reenable sync flood after ECC init | Timothy Pearson |
2016-04-08 | nb/amd/mct_ddr3: Add MCE reporting logic | Timothy Pearson |
2016-04-08 | nb/amd/amdfam10: Only flag machine check exception if valid bit is set | Timothy Pearson |
2016-04-08 | nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level | Timothy Pearson |
2016-04-01 | nb/amd/mct_ddr3: Fix revision mask for DR processors | Timothy Pearson |
2016-03-31 | nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage | Timothy Pearson |
2016-03-31 | nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs | Timothy Pearson |
2016-03-31 | nb/amd/mct_ddr3: Disable MCE framework during DRAM training | Timothy Pearson |
2016-03-30 | nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed | Timothy Pearson |
2016-03-30 | northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity) | Damien Zammit |
2016-03-28 | nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D() | Timothy Pearson |
2016-03-26 | nb/amd/amdmct: Select max_lanes based on ECC presence or absence | Damien Zammit |
2016-03-24 | nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values | Timothy Pearson |
2016-03-23 | nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_... | Timothy Pearson |
2016-03-21 | nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set | Timothy Pearson |
2016-03-13 | nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training | Timothy Pearson |
2016-03-12 | nb/amd/mct_ddr3: Consolidate duplicated code | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15 | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Require minumum training quality for both read and write | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks | Timothy Pearson |
2016-03-11 | nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop | Timothy Pearson |
2016-02-19 | nb/amd/amdmct: Add socket specific configuration for FM2 | Damien Zammit |
2016-02-05 | nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h | Timothy Pearson |
2016-02-05 | nb/amd/mct_ddr3: Work around RDIMM training failure | Timothy Pearson |
2016-02-02 | src: Fix various spelling and whitespace issues. | Martin Roth |