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Some coreboot project code with my work
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northbridge
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intel
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gm45
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raminit_read_write_training.c
Age
Commit message (
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Author
2020-04-05
src/northbridge: Use SPDX for GPL-2.0-only files
Angel Pons
2020-03-17
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2019-10-27
src/[northbridge,security]: change "unsigned" to "unsigned int"
Martin Roth
2019-03-04
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2017-04-19
nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUP
Nico Huber
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2013-05-22
intel/gm45: Add more debug output to read/write training
Nico Huber
2013-05-22
intel/gm45: Handle overflows during DDR3 write training
Nico Huber
2013-05-22
intel/gm45: Refactor DDR3 write training
Nico Huber
2013-05-22
intel/gm45: Handle overflows during DDR3 read training
Nico Huber
2013-05-22
intel/gm45: Refactor DDR3 read training
Nico Huber
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-11-27
intel/gm45: new northbridge
Patrick Georgi