index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
/
intel
/
gm45
/
stage_cache.c
Age
Commit message (
Expand
)
Author
2019-03-04
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-01-24
nb/intel/gm45: Put stage cache in TSEG
Arthur Heymans