| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-11-27 | intel/gm45: new northbridge | Patrick Georgi | |
| The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
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