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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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path:
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src
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northbridge
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intel
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sandybridge
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chip.h
Age
Commit message (
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Author
2020-03-18
nb/intel/sandybridge: Tidy up code and comments
Angel Pons
2020-03-17
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2019-05-13
nb/intel/sandybridge: Migrate MRC settings to devicetree
Patrick Rudolph
2016-06-12
nb/intel/raminit (native): Read PCI mmio size from devicetree
Patrick Rudolph
2016-02-28
northbridge/intel: add missing #include guards
Iru Cai
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-02-17
sandybridge/raminit: Get max mem clock from devicetree
Alexandru Gagniuc
2014-09-13
intel/gma: consolidate vbt code
Vladimir Serbinenko
2014-07-29
ivybridge: LVDS gfx init.
Vladimir Serbinenko
2014-07-08
northbridge: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-08-22
Auto-declare chip_operations
Kyösti Mälkki
2012-05-01
Update ivybridge graphics initialization
Duncan Laurie
2012-04-05
Add support for Intel Sandybridge CPU (northbridge part)
Stefan Reinauer