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coreboot
2560p
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autoport-hsw
broadwell_refcode
e6230
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haswell-mrc
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Some coreboot project code with my work
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northbridge
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intel
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sandybridge
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northbridge.c
Age
Commit message (
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Author
2012-11-28
Remove assembly coded log2 function
Ronald G. Minnich
2012-08-08
Cleanup coreboot memory table includes
Kyösti Mälkki
2012-08-07
Sandy/Ivy Bridge and Cougar/Panther Point: Fix names
Stefan Reinauer
2012-08-01
Intel and GFXUMA: drop redundant use of lb_add_memory_range()
Kyösti Mälkki
2012-08-01
Intel Sandybridge and UMA: use mmio_resource()
Kyösti Mälkki
2012-08-01
Intel Sandybridge: add reserved memory as resources
Kyösti Mälkki
2012-07-24
Ivybridge: fix workaround and enable PAIR
Duncan Laurie
2012-07-24
CPU: Add basic support for Nominal Configurable TDP
Duncan Laurie
2012-07-24
SandyBridge: Add another PCI device ID for northbridge
Walter Murphy
2012-07-16
Define global uma_memory variables
Kyösti Mälkki
2012-05-11
Hook up MRC cache update
Stefan Reinauer
2012-05-11
Rework Sandybridge MRC cache handling
Stefan Reinauer
2012-05-08
Clean up #ifs
Patrick Georgi
2012-05-01
Modify DMI init for IvyBridge
Vincent Palatin
2012-04-05
Add support for Intel Sandybridge CPU (northbridge part)
Stefan Reinauer
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