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path: root/src/northbridge/intel/sandybridge/raminit_common.c
AgeCommit message (Expand)Author
2020-07-26nb/intel/sandybridge: Add missing includesElyes HAOUAS
2020-05-21nb/intel/sandybridge: Use the new IOSAV struct APIAngel Pons
2020-05-21nb/intel/sandybridge: Drop unused parametersAngel Pons
2020-05-21nb/intel/sandybridge: Redefine IOSAV_SUBSEQUENCEAngel Pons
2020-05-21nb/intel/sandybridge: Truncate IOSAV subseq gapsAngel Pons
2020-05-21nb/intel/sandybridge: Replace macros with functionsAngel Pons
2020-05-21nb/intel/sandybridge: Refactor IOSAV_RUN_ONCEAngel Pons
2020-05-21nb/intel/sandybridge: Refactor IOSAV_SUBSEQUENCE againAngel Pons
2020-05-18nb/intel/sandybridge: Use or-based logic for RANKSELAngel Pons
2020-05-18nb/intel/sandybridge: Program IOSAV with macrosAngel Pons
2020-05-18nb/intel/sandybridge: Add and use BROADCAST_CH for IOSAVAngel Pons
2020-05-12nb/intel/sandybridge: Reorder IOSAV writesAngel Pons
2020-05-12nb/intel/sandybridge: Reorder register writeAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-19nb/intel/sandybridge: Refactor get_mem_min_tckAngel Pons
2020-04-14nb/intel/sandybridge/raminit: Add ECC supportPatrick Rudolph
2020-04-14nb/intel/sandybridge/raminit: Add ECC detection supportPatrick Rudolph
2020-03-26nb/intel/sandybridge: Use macros for JEDEC commandsAngel Pons
2020-03-26nb/intel/sandybridge: Correct TC_DTP handlingAngel Pons
2020-03-26nb/intel/sandybridge: Add and use TC_DTP definitionAngel Pons
2020-03-26nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macroAngel Pons
2020-03-26nb/intel/sandybridge: Update commentAngel Pons
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
2020-03-23nb/intel/sandybridge: Do not define tables in a headerAngel Pons
2020-03-22nb/intel/sandybridge: Drop spurious register writeAngel Pons
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-01-27nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE defineFelix Held
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
2020-01-15nb/intel/sandybridge: Repurpose HOST_BRIDGE macroAngel Pons
2020-01-14nb/intel/sandybridge: Drop 'or zero' instancesAngel Pons
2020-01-11nb/intel/sandybridge: Tidy up raminit codeAngel Pons
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
2020-01-09nb/intel/sandybridge: Make MCHBAR arithmetics consistentAngel Pons
2020-01-01nb/intel/sandybridge: replace .val_4028 with .io_latencyFelix Held
2020-01-01nb/intel/sandybridge: Make `PM_PDWN_Config` uppercaseAngel Pons
2020-01-01nb/intel/sandybridge: add and use memory thermal configuration registersFelix Held
2020-01-01nb/intel/sandybridge: add and use ME stolen memory and lock bit definesFelix Held
2020-01-01nb/intel/sandybridge: add and use more MCHBAR register definesFelix Held
2020-01-01nb/intel/sandybridge: use MESEG register names from datasheetFelix Held
2019-12-29nb/intel/sandybridge: simplify ME lock and memory enable bit writeFelix Held
2019-12-29nb/intel/sandybridge: add and use defines for ME base and mask registersFelix Held
2019-12-29nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registersFelix Held
2019-12-20{nb,soc}: Replace min/max() with MIN/MAX()Elyes HAOUAS
2019-06-03nb/intel/sandybridge: Remove variable set but not usedElyes HAOUAS
2019-05-29intel/sandybridge: Make timC training more robust.Tobias Diedrich
2019-05-07{src,util}: Remove duplicated includesElyes HAOUAS
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