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path: root/src/northbridge/intel/sandybridge/raminit_mrc.c
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2020-05-09vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()Julius Werner
vboot_recovery_mode_enabled() was recently changed to assert() when it is called before vboot logic has run, because we cannot determine whether we're going to be in recovery mode at that point and we wanted to flush out existing uses that pretended that we could. Turns out there are a bunch of uses like that, and there is some code that is shared across configurations that can and those that can't. This patch cleans them up to either remove checks that cannot return true, or add explicit Kconfig guards to clarify that the code is shared. This means that using a separate recovery MRC cache is no longer supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already been broken with CB:38780, but with this patch those boards will boot again using their normal MRC caches rather than just die). Skipping the MRC cache and always regenerating from scratch in recovery mode is likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE. For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and that is unlikely to change in the future so we will just hardcode that fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed to work around this issue). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
Note that pei_data.h uses the BSD 3-Clause license: https://opensource.org/licenses/BSD-3-Clause Change-Id: I904b343283239af4fdee583bcbea757f59a0cca7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-20nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons
Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
- Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07src/nb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I7dd6dd8e8debe1b6419625fca38670be375ef581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
While we are at it, also: - Rename related variables to match the register names. - Update some comments to better reflect what some registers are about. - Add various FIXME comments on registers that seem to be used wrongly. With BUILD_TIMELESS=1, this commit does not change the coreboot build of: - Asus P8H61-M PRO with native raminit. - Gigabyte GA-H61MA-D3V with native raminit. - Lenovo Thinkpad X230 with native raminit. - Lenovo Thinkpad X220 with MRC raminit. Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-06drivers/pc80/rtc: Swap cmos_write32() parameter orderKyösti Mälkki
Make it consistent with the more used cmos_write(). Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-01nb/intel/sandybridge: Use the MC_BIOS_DATA defineAngel Pons
Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: add and use more MCHBAR register definesFelix Held
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-27arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki
There are no symmetrical headerfiles for other arch/ and after ROMCC_BOOTBLOCK and walkcbfs() removal this file ended up empty. Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-18nb/intel/sandybridge/mrc: Handle P2P disabling via devicetreeNico Huber
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-173rdparty/blobs: Update submodule, SNB improvementsArthur Heymans
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22post_code: add post code for invalid vendor binaryKeith Short
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-15src/northbridge: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-13nb/intel/sandybridge: Migrate MRC settings to devicetreePatrick Rudolph
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree. This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure. The followup commit will migrate to devicetree.cb. Tested on Lenovo T520, boots MRC path with the new devicetree settings. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13mb/samsung/lumpy: Move onboard SPD to second channelPatrick Rudolph
Move the onboard SPD to second channel as native raminit does and workaround mrc expecations in northbridge code. Required to move pei data to devicetree and to use the same code for mrc and native raminit. Tested on Lenovo T520: Other fields then spd_data[0] are ignored. Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06src: Remove unused include <halt.h>Elyes HAOUAS
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29nb/intel/sandybridge: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: Ic4716a3bb1dc6c6b29a028fc0ab28f9195f08416 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23nb/intel/sandybridge: add pch.h includePatrick Georgi
Fixes src/northbridge/intel/sandybridge/raminit_mrc.c:286:3: error: implicit declaration of function 'enable_usb_bar' Change-Id: I48bf59c56b518477a3fc0d75902fc58df6b7def7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32400 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINITKyösti Mälkki
Fail builds if MRC blobs pool heap would get corrupted by CAR relocatable data from coreboot proper. Add runtime logging how much pool was required. Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31150 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06usbdebug: Refactor init callsKyösti Mälkki
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier
Commit ef8c559e537ed10d8054ca6a72ca50e0531fde95 [nb/intel/sandybridge/report_platform: Move remaining code to sb folder] moved reporting code to the southbridge, but missed a reference in the non-default MRC raminit path (so testing missed it). Remove invalid reference to fix compilation error. Test: build google/link with MRC raminit option selected Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
Change-Id: I8174d7b40008cfe4fba10fde4670682aac0ad078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Tested working on Lenovo Thinkpad x220, mrc_cache region gets written and S3 resume still works fine. Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-09-27northbridge/sandybridge/raminit_mrc.c: fix missing includeMatt DeVillier
Compilation (w/o native raminit) fails due to missing include Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/16735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
Remove code duplication and use the common function store_current_mrc_cache instead. No functionality is changed. Tested on Sandybridge Lenovo T520. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15074 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-09northbridge/intel/sandybridge: Enable PEG clock-gating on demandPatrick Rudolph
Activate PEG clock-gating only if all PEG devices are disabled. Fixes system hang when trying to access PEG registers. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11059 Tested-by: build bot (Jenkins)
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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